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stm32f722xx.h
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1
34#ifndef __STM32F722xx_H
35#define __STM32F722xx_H
36
37#ifdef __cplusplus
38 extern "C" {
39#endif /* __cplusplus */
40
49typedef enum
50{
51/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
52 NonMaskableInt_IRQn = -14,
53 MemoryManagement_IRQn = -12,
54 BusFault_IRQn = -11,
55 UsageFault_IRQn = -10,
56 SVCall_IRQn = -5,
57 DebugMonitor_IRQn = -4,
58 PendSV_IRQn = -2,
59 SysTick_IRQn = -1,
60/****** STM32 specific Interrupt Numbers **********************************************************************/
61 WWDG_IRQn = 0,
62 PVD_IRQn = 1,
63 TAMP_STAMP_IRQn = 2,
64 RTC_WKUP_IRQn = 3,
65 FLASH_IRQn = 4,
66 RCC_IRQn = 5,
67 EXTI0_IRQn = 6,
68 EXTI1_IRQn = 7,
69 EXTI2_IRQn = 8,
70 EXTI3_IRQn = 9,
71 EXTI4_IRQn = 10,
72 DMA1_Stream0_IRQn = 11,
73 DMA1_Stream1_IRQn = 12,
74 DMA1_Stream2_IRQn = 13,
75 DMA1_Stream3_IRQn = 14,
76 DMA1_Stream4_IRQn = 15,
77 DMA1_Stream5_IRQn = 16,
78 DMA1_Stream6_IRQn = 17,
79 ADC_IRQn = 18,
80 CAN1_TX_IRQn = 19,
81 CAN1_RX0_IRQn = 20,
82 CAN1_RX1_IRQn = 21,
83 CAN1_SCE_IRQn = 22,
84 EXTI9_5_IRQn = 23,
85 TIM1_BRK_TIM9_IRQn = 24,
86 TIM1_UP_TIM10_IRQn = 25,
87 TIM1_TRG_COM_TIM11_IRQn = 26,
88 TIM1_CC_IRQn = 27,
89 TIM2_IRQn = 28,
90 TIM3_IRQn = 29,
91 TIM4_IRQn = 30,
92 I2C1_EV_IRQn = 31,
93 I2C1_ER_IRQn = 32,
94 I2C2_EV_IRQn = 33,
95 I2C2_ER_IRQn = 34,
96 SPI1_IRQn = 35,
97 SPI2_IRQn = 36,
98 USART1_IRQn = 37,
99 USART2_IRQn = 38,
100 USART3_IRQn = 39,
101 EXTI15_10_IRQn = 40,
102 RTC_Alarm_IRQn = 41,
103 OTG_FS_WKUP_IRQn = 42,
104 TIM8_BRK_TIM12_IRQn = 43,
105 TIM8_UP_TIM13_IRQn = 44,
106 TIM8_TRG_COM_TIM14_IRQn = 45,
107 TIM8_CC_IRQn = 46,
108 DMA1_Stream7_IRQn = 47,
109 FMC_IRQn = 48,
110 SDMMC1_IRQn = 49,
111 TIM5_IRQn = 50,
112 SPI3_IRQn = 51,
113 UART4_IRQn = 52,
114 UART5_IRQn = 53,
115 TIM6_DAC_IRQn = 54,
116 TIM7_IRQn = 55,
117 DMA2_Stream0_IRQn = 56,
118 DMA2_Stream1_IRQn = 57,
119 DMA2_Stream2_IRQn = 58,
120 DMA2_Stream3_IRQn = 59,
121 DMA2_Stream4_IRQn = 60,
122 ETH_IRQn = 61,
123 ETH_WKUP_IRQn = 62,
124 OTG_FS_IRQn = 67,
125 DMA2_Stream5_IRQn = 68,
126 DMA2_Stream6_IRQn = 69,
127 DMA2_Stream7_IRQn = 70,
128 USART6_IRQn = 71,
129 I2C3_EV_IRQn = 72,
130 I2C3_ER_IRQn = 73,
131 OTG_HS_EP1_OUT_IRQn = 74,
132 OTG_HS_EP1_IN_IRQn = 75,
133 OTG_HS_WKUP_IRQn = 76,
134 OTG_HS_IRQn = 77,
135 RNG_IRQn = 80,
136 FPU_IRQn = 81,
137 UART7_IRQn = 82,
138 UART8_IRQn = 83,
139 SPI4_IRQn = 84,
140 SPI5_IRQn = 85,
141 SAI1_IRQn = 87,
142 SAI2_IRQn = 91,
143 QUADSPI_IRQn = 92,
144 LPTIM1_IRQn = 93,
145 SDMMC2_IRQn = 103,
146} IRQn_Type;
147
155#define __CM7_REV 0x0100U
156#define __MPU_PRESENT 1
157#define __NVIC_PRIO_BITS 4
158#define __Vendor_SysTickConfig 0
159#define __FPU_PRESENT 1
160#define __ICACHE_PRESENT 1
161#define __DCACHE_PRESENT 1
162#include "core_cm7.h"
165#include "system_stm32f7xx.h"
166#include <stdint.h>
167
176typedef struct
177{
178 __IO uint32_t SR;
179 __IO uint32_t CR1;
180 __IO uint32_t CR2;
181 __IO uint32_t SMPR1;
182 __IO uint32_t SMPR2;
183 __IO uint32_t JOFR1;
184 __IO uint32_t JOFR2;
185 __IO uint32_t JOFR3;
186 __IO uint32_t JOFR4;
187 __IO uint32_t HTR;
188 __IO uint32_t LTR;
189 __IO uint32_t SQR1;
190 __IO uint32_t SQR2;
191 __IO uint32_t SQR3;
192 __IO uint32_t JSQR;
193 __IO uint32_t JDR1;
194 __IO uint32_t JDR2;
195 __IO uint32_t JDR3;
196 __IO uint32_t JDR4;
197 __IO uint32_t DR;
198} ADC_TypeDef;
199
200typedef struct
201{
202 __IO uint32_t CSR;
203 __IO uint32_t CCR;
204 __IO uint32_t CDR;
206} ADC_Common_TypeDef;
207
208
213typedef struct
214{
215 __IO uint32_t TIR;
216 __IO uint32_t TDTR;
217 __IO uint32_t TDLR;
218 __IO uint32_t TDHR;
219} CAN_TxMailBox_TypeDef;
220
225typedef struct
226{
227 __IO uint32_t RIR;
228 __IO uint32_t RDTR;
229 __IO uint32_t RDLR;
230 __IO uint32_t RDHR;
231} CAN_FIFOMailBox_TypeDef;
232
237typedef struct
238{
239 __IO uint32_t FR1;
240 __IO uint32_t FR2;
241} CAN_FilterRegister_TypeDef;
242
247typedef struct
248{
249 __IO uint32_t MCR;
250 __IO uint32_t MSR;
251 __IO uint32_t TSR;
252 __IO uint32_t RF0R;
253 __IO uint32_t RF1R;
254 __IO uint32_t IER;
255 __IO uint32_t ESR;
256 __IO uint32_t BTR;
257 uint32_t RESERVED0[88];
258 CAN_TxMailBox_TypeDef sTxMailBox[3];
259 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
260 uint32_t RESERVED1[12];
261 __IO uint32_t FMR;
262 __IO uint32_t FM1R;
263 uint32_t RESERVED2;
264 __IO uint32_t FS1R;
265 uint32_t RESERVED3;
266 __IO uint32_t FFA1R;
267 uint32_t RESERVED4;
268 __IO uint32_t FA1R;
269 uint32_t RESERVED5[8];
270 CAN_FilterRegister_TypeDef sFilterRegister[28];
271} CAN_TypeDef;
272
273
278typedef struct
279{
280 __IO uint32_t DR;
281 __IO uint8_t IDR;
282 uint8_t RESERVED0;
283 uint16_t RESERVED1;
284 __IO uint32_t CR;
285 uint32_t RESERVED2;
286 __IO uint32_t INIT;
287 __IO uint32_t POL;
288} CRC_TypeDef;
289
294typedef struct
295{
296 __IO uint32_t CR;
297 __IO uint32_t SWTRIGR;
298 __IO uint32_t DHR12R1;
299 __IO uint32_t DHR12L1;
300 __IO uint32_t DHR8R1;
301 __IO uint32_t DHR12R2;
302 __IO uint32_t DHR12L2;
303 __IO uint32_t DHR8R2;
304 __IO uint32_t DHR12RD;
305 __IO uint32_t DHR12LD;
306 __IO uint32_t DHR8RD;
307 __IO uint32_t DOR1;
308 __IO uint32_t DOR2;
309 __IO uint32_t SR;
310} DAC_TypeDef;
311
312
317typedef struct
318{
319 __IO uint32_t IDCODE;
320 __IO uint32_t CR;
321 __IO uint32_t APB1FZ;
322 __IO uint32_t APB2FZ;
323}DBGMCU_TypeDef;
324
325
330typedef struct
331{
332 __IO uint32_t CR;
333 __IO uint32_t NDTR;
334 __IO uint32_t PAR;
335 __IO uint32_t M0AR;
336 __IO uint32_t M1AR;
337 __IO uint32_t FCR;
338} DMA_Stream_TypeDef;
339
340typedef struct
341{
342 __IO uint32_t LISR;
343 __IO uint32_t HISR;
344 __IO uint32_t LIFCR;
345 __IO uint32_t HIFCR;
346} DMA_TypeDef;
347
348
353typedef struct
354{
355 __IO uint32_t IMR;
356 __IO uint32_t EMR;
357 __IO uint32_t RTSR;
358 __IO uint32_t FTSR;
359 __IO uint32_t SWIER;
360 __IO uint32_t PR;
361} EXTI_TypeDef;
362
367typedef struct
368{
369 __IO uint32_t ACR;
370 __IO uint32_t KEYR;
371 __IO uint32_t OPTKEYR;
372 __IO uint32_t SR;
373 __IO uint32_t CR;
374 __IO uint32_t OPTCR;
375 __IO uint32_t OPTCR1;
376 __IO uint32_t OPTCR2;
377} FLASH_TypeDef;
378
379
380
385typedef struct
386{
387 __IO uint32_t BTCR[8];
388} FMC_Bank1_TypeDef;
389
394typedef struct
395{
396 __IO uint32_t BWTR[7];
397} FMC_Bank1E_TypeDef;
398
403typedef struct
404{
405 __IO uint32_t PCR;
406 __IO uint32_t SR;
407 __IO uint32_t PMEM;
408 __IO uint32_t PATT;
409 uint32_t RESERVED0;
410 __IO uint32_t ECCR;
411} FMC_Bank3_TypeDef;
412
417typedef struct
418{
419 __IO uint32_t SDCR[2];
420 __IO uint32_t SDTR[2];
421 __IO uint32_t SDCMR;
422 __IO uint32_t SDRTR;
423 __IO uint32_t SDSR;
424} FMC_Bank5_6_TypeDef;
425
426
431typedef struct
432{
433 __IO uint32_t MODER;
434 __IO uint32_t OTYPER;
435 __IO uint32_t OSPEEDR;
436 __IO uint32_t PUPDR;
437 __IO uint32_t IDR;
438 __IO uint32_t ODR;
439 __IO uint32_t BSRR;
440 __IO uint32_t LCKR;
441 __IO uint32_t AFR[2];
442} GPIO_TypeDef;
443
448typedef struct
449{
450 __IO uint32_t MEMRMP;
451 __IO uint32_t PMC;
452 __IO uint32_t EXTICR[4];
453 uint32_t RESERVED[2];
454 __IO uint32_t CMPCR;
455} SYSCFG_TypeDef;
456
461typedef struct
462{
463 __IO uint32_t CR1;
464 __IO uint32_t CR2;
465 __IO uint32_t OAR1;
466 __IO uint32_t OAR2;
467 __IO uint32_t TIMINGR;
468 __IO uint32_t TIMEOUTR;
469 __IO uint32_t ISR;
470 __IO uint32_t ICR;
471 __IO uint32_t PECR;
472 __IO uint32_t RXDR;
473 __IO uint32_t TXDR;
474} I2C_TypeDef;
475
480typedef struct
481{
482 __IO uint32_t KR;
483 __IO uint32_t PR;
484 __IO uint32_t RLR;
485 __IO uint32_t SR;
486 __IO uint32_t WINR;
487} IWDG_TypeDef;
488
489
490
495typedef struct
496{
497 __IO uint32_t CR1;
498 __IO uint32_t CSR1;
499 __IO uint32_t CR2;
500 __IO uint32_t CSR2;
501} PWR_TypeDef;
502
503
508typedef struct
509{
510 __IO uint32_t CR;
511 __IO uint32_t PLLCFGR;
512 __IO uint32_t CFGR;
513 __IO uint32_t CIR;
514 __IO uint32_t AHB1RSTR;
515 __IO uint32_t AHB2RSTR;
516 __IO uint32_t AHB3RSTR;
517 uint32_t RESERVED0;
518 __IO uint32_t APB1RSTR;
519 __IO uint32_t APB2RSTR;
520 uint32_t RESERVED1[2];
521 __IO uint32_t AHB1ENR;
522 __IO uint32_t AHB2ENR;
523 __IO uint32_t AHB3ENR;
524 uint32_t RESERVED2;
525 __IO uint32_t APB1ENR;
526 __IO uint32_t APB2ENR;
527 uint32_t RESERVED3[2];
528 __IO uint32_t AHB1LPENR;
529 __IO uint32_t AHB2LPENR;
530 __IO uint32_t AHB3LPENR;
531 uint32_t RESERVED4;
532 __IO uint32_t APB1LPENR;
533 __IO uint32_t APB2LPENR;
534 uint32_t RESERVED5[2];
535 __IO uint32_t BDCR;
536 __IO uint32_t CSR;
537 uint32_t RESERVED6[2];
538 __IO uint32_t SSCGR;
539 __IO uint32_t PLLI2SCFGR;
540 __IO uint32_t PLLSAICFGR;
541 __IO uint32_t DCKCFGR1;
542 __IO uint32_t DCKCFGR2;
544} RCC_TypeDef;
545
550typedef struct
551{
552 __IO uint32_t TR;
553 __IO uint32_t DR;
554 __IO uint32_t CR;
555 __IO uint32_t ISR;
556 __IO uint32_t PRER;
557 __IO uint32_t WUTR;
558 uint32_t reserved;
559 __IO uint32_t ALRMAR;
560 __IO uint32_t ALRMBR;
561 __IO uint32_t WPR;
562 __IO uint32_t SSR;
563 __IO uint32_t SHIFTR;
564 __IO uint32_t TSTR;
565 __IO uint32_t TSDR;
566 __IO uint32_t TSSSR;
567 __IO uint32_t CALR;
568 __IO uint32_t TAMPCR;
569 __IO uint32_t ALRMASSR;
570 __IO uint32_t ALRMBSSR;
571 __IO uint32_t OR;
572 __IO uint32_t BKP0R;
573 __IO uint32_t BKP1R;
574 __IO uint32_t BKP2R;
575 __IO uint32_t BKP3R;
576 __IO uint32_t BKP4R;
577 __IO uint32_t BKP5R;
578 __IO uint32_t BKP6R;
579 __IO uint32_t BKP7R;
580 __IO uint32_t BKP8R;
581 __IO uint32_t BKP9R;
582 __IO uint32_t BKP10R;
583 __IO uint32_t BKP11R;
584 __IO uint32_t BKP12R;
585 __IO uint32_t BKP13R;
586 __IO uint32_t BKP14R;
587 __IO uint32_t BKP15R;
588 __IO uint32_t BKP16R;
589 __IO uint32_t BKP17R;
590 __IO uint32_t BKP18R;
591 __IO uint32_t BKP19R;
592 __IO uint32_t BKP20R;
593 __IO uint32_t BKP21R;
594 __IO uint32_t BKP22R;
595 __IO uint32_t BKP23R;
596 __IO uint32_t BKP24R;
597 __IO uint32_t BKP25R;
598 __IO uint32_t BKP26R;
599 __IO uint32_t BKP27R;
600 __IO uint32_t BKP28R;
601 __IO uint32_t BKP29R;
602 __IO uint32_t BKP30R;
603 __IO uint32_t BKP31R;
604} RTC_TypeDef;
605
606
611typedef struct
612{
613 __IO uint32_t GCR;
614} SAI_TypeDef;
615
616typedef struct
617{
618 __IO uint32_t CR1;
619 __IO uint32_t CR2;
620 __IO uint32_t FRCR;
621 __IO uint32_t SLOTR;
622 __IO uint32_t IMR;
623 __IO uint32_t SR;
624 __IO uint32_t CLRFR;
625 __IO uint32_t DR;
626} SAI_Block_TypeDef;
627
628
633typedef struct
634{
635 __IO uint32_t POWER;
636 __IO uint32_t CLKCR;
637 __IO uint32_t ARG;
638 __IO uint32_t CMD;
639 __I uint32_t RESPCMD;
640 __I uint32_t RESP1;
641 __I uint32_t RESP2;
642 __I uint32_t RESP3;
643 __I uint32_t RESP4;
644 __IO uint32_t DTIMER;
645 __IO uint32_t DLEN;
646 __IO uint32_t DCTRL;
647 __I uint32_t DCOUNT;
648 __I uint32_t STA;
649 __IO uint32_t ICR;
650 __IO uint32_t MASK;
651 uint32_t RESERVED0[2];
652 __I uint32_t FIFOCNT;
653 uint32_t RESERVED1[13];
654 __IO uint32_t FIFO;
655} SDMMC_TypeDef;
656
661typedef struct
662{
663 __IO uint32_t CR1;
664 __IO uint32_t CR2;
665 __IO uint32_t SR;
666 __IO uint32_t DR;
667 __IO uint32_t CRCPR;
668 __IO uint32_t RXCRCR;
669 __IO uint32_t TXCRCR;
670 __IO uint32_t I2SCFGR;
671 __IO uint32_t I2SPR;
672} SPI_TypeDef;
673
678typedef struct
679{
680 __IO uint32_t CR;
681 __IO uint32_t DCR;
682 __IO uint32_t SR;
683 __IO uint32_t FCR;
684 __IO uint32_t DLR;
685 __IO uint32_t CCR;
686 __IO uint32_t AR;
687 __IO uint32_t ABR;
688 __IO uint32_t DR;
689 __IO uint32_t PSMKR;
690 __IO uint32_t PSMAR;
691 __IO uint32_t PIR;
692 __IO uint32_t LPTR;
693} QUADSPI_TypeDef;
694
699typedef struct
700{
701 __IO uint32_t CR1;
702 __IO uint32_t CR2;
703 __IO uint32_t SMCR;
704 __IO uint32_t DIER;
705 __IO uint32_t SR;
706 __IO uint32_t EGR;
707 __IO uint32_t CCMR1;
708 __IO uint32_t CCMR2;
709 __IO uint32_t CCER;
710 __IO uint32_t CNT;
711 __IO uint32_t PSC;
712 __IO uint32_t ARR;
713 __IO uint32_t RCR;
714 __IO uint32_t CCR1;
715 __IO uint32_t CCR2;
716 __IO uint32_t CCR3;
717 __IO uint32_t CCR4;
718 __IO uint32_t BDTR;
719 __IO uint32_t DCR;
720 __IO uint32_t DMAR;
721 __IO uint32_t OR;
722 __IO uint32_t CCMR3;
723 __IO uint32_t CCR5;
724 __IO uint32_t CCR6;
726} TIM_TypeDef;
727
731typedef struct
732{
733 __IO uint32_t ISR;
734 __IO uint32_t ICR;
735 __IO uint32_t IER;
736 __IO uint32_t CFGR;
737 __IO uint32_t CR;
738 __IO uint32_t CMP;
739 __IO uint32_t ARR;
740 __IO uint32_t CNT;
741} LPTIM_TypeDef;
742
743
748typedef struct
749{
750 __IO uint32_t CR1;
751 __IO uint32_t CR2;
752 __IO uint32_t CR3;
753 __IO uint32_t BRR;
754 __IO uint32_t GTPR;
755 __IO uint32_t RTOR;
756 __IO uint32_t RQR;
757 __IO uint32_t ISR;
758 __IO uint32_t ICR;
759 __IO uint32_t RDR;
760 __IO uint32_t TDR;
761} USART_TypeDef;
762
763
768typedef struct
769{
770 __IO uint32_t CR;
771 __IO uint32_t CFR;
772 __IO uint32_t SR;
773} WWDG_TypeDef;
774
775
780typedef struct
781{
782 __IO uint32_t CR;
783 __IO uint32_t SR;
784 __IO uint32_t DR;
785} RNG_TypeDef;
786
794typedef struct
795{
796 __IO uint32_t GOTGCTL;
797 __IO uint32_t GOTGINT;
798 __IO uint32_t GAHBCFG;
799 __IO uint32_t GUSBCFG;
800 __IO uint32_t GRSTCTL;
801 __IO uint32_t GINTSTS;
802 __IO uint32_t GINTMSK;
803 __IO uint32_t GRXSTSR;
804 __IO uint32_t GRXSTSP;
805 __IO uint32_t GRXFSIZ;
806 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
807 __IO uint32_t HNPTXSTS;
808 uint32_t Reserved30[2];
809 __IO uint32_t GCCFG;
810 __IO uint32_t CID;
811 uint32_t Reserved5[3];
812 __IO uint32_t GHWCFG3;
813 uint32_t Reserved6;
814 __IO uint32_t GLPMCFG;
815 uint32_t Reserved7;
816 __IO uint32_t GDFIFOCFG;
817 uint32_t Reserved43[40];
818 __IO uint32_t HPTXFSIZ;
819 __IO uint32_t DIEPTXF[0x0F];
820} USB_OTG_GlobalTypeDef;
821
822
826typedef struct
827{
828 __IO uint32_t DCFG;
829 __IO uint32_t DCTL;
830 __IO uint32_t DSTS;
831 uint32_t Reserved0C;
832 __IO uint32_t DIEPMSK;
833 __IO uint32_t DOEPMSK;
834 __IO uint32_t DAINT;
835 __IO uint32_t DAINTMSK;
836 uint32_t Reserved20;
837 uint32_t Reserved9;
838 __IO uint32_t DVBUSDIS;
839 __IO uint32_t DVBUSPULSE;
840 __IO uint32_t DTHRCTL;
841 __IO uint32_t DIEPEMPMSK;
842 __IO uint32_t DEACHINT;
843 __IO uint32_t DEACHMSK;
844 uint32_t Reserved40;
845 __IO uint32_t DINEP1MSK;
846 uint32_t Reserved44[15];
847 __IO uint32_t DOUTEP1MSK;
848} USB_OTG_DeviceTypeDef;
849
850
854typedef struct
855{
856 __IO uint32_t DIEPCTL;
857 uint32_t Reserved04;
858 __IO uint32_t DIEPINT;
859 uint32_t Reserved0C;
860 __IO uint32_t DIEPTSIZ;
861 __IO uint32_t DIEPDMA;
862 __IO uint32_t DTXFSTS;
863 uint32_t Reserved18;
864} USB_OTG_INEndpointTypeDef;
865
866
870typedef struct
871{
872 __IO uint32_t DOEPCTL;
873 uint32_t Reserved04;
874 __IO uint32_t DOEPINT;
875 uint32_t Reserved0C;
876 __IO uint32_t DOEPTSIZ;
877 __IO uint32_t DOEPDMA;
878 uint32_t Reserved18[2];
879} USB_OTG_OUTEndpointTypeDef;
880
881
885typedef struct
886{
887 __IO uint32_t HCFG;
888 __IO uint32_t HFIR;
889 __IO uint32_t HFNUM;
890 uint32_t Reserved40C;
891 __IO uint32_t HPTXSTS;
892 __IO uint32_t HAINT;
893 __IO uint32_t HAINTMSK;
894} USB_OTG_HostTypeDef;
895
899typedef struct
900{
901 __IO uint32_t HCCHAR;
902 __IO uint32_t HCSPLT;
903 __IO uint32_t HCINT;
904 __IO uint32_t HCINTMSK;
905 __IO uint32_t HCTSIZ;
906 __IO uint32_t HCDMA;
907 uint32_t Reserved[2];
908} USB_OTG_HostChannelTypeDef;
919#define RAMITCM_BASE 0x00000000UL
920#define FLASHITCM_BASE 0x00200000UL
921#define FLASHAXI_BASE 0x08000000UL
922#define RAMDTCM_BASE 0x20000000UL
923#define PERIPH_BASE 0x40000000UL
924#define BKPSRAM_BASE 0x40024000UL
925#define QSPI_BASE 0x90000000UL
926#define FMC_R_BASE 0xA0000000UL
927#define QSPI_R_BASE 0xA0001000UL
928#define SRAM1_BASE 0x20010000UL
929#define SRAM2_BASE 0x2003C000UL
930#define FLASH_END 0x0807FFFFUL
931#define FLASH_OTP_BASE 0x1FF07800UL
932#define FLASH_OTP_END 0x1FF07A0FUL
934/* Legacy define */
935#define FLASH_BASE FLASHAXI_BASE
936
938#define APB1PERIPH_BASE PERIPH_BASE
939#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
940#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
941#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
942
944#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
945#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
946#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
947#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
948#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
949#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
950#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)
951#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)
952#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)
953#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)
954#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
955#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
956#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
957#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
958#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
959#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
960#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
961#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
962#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
963#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
964#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
965#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
966#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
967#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
968#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
969#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)
970#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)
971
973#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)
974#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)
975#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)
976#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)
977#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00UL)
978#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)
979#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)
980#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)
981#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL)
982#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL)
983#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
984#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)
985#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)
986#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)
987#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)
988#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)
989#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)
990#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)
991#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)
992#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL)
993#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
994#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
995#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
996#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
998#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)
999#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)
1000#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)
1001#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)
1002#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)
1003#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)
1004#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)
1005#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)
1006#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)
1007#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
1008#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)
1009#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)
1010#define UID_BASE 0x1FF07A10UL
1011#define FLASHSIZE_BASE 0x1FF07A22UL
1012#define PACKAGE_BASE 0x1FF07BF0UL
1013/* Legacy define */
1014#define PACKAGESIZE_BASE PACKAGE_BASE
1015
1016#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)
1017#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
1018#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
1019#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
1020#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
1021#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
1022#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
1023#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
1024#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
1025#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)
1026#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
1027#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
1028#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
1029#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
1030#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
1031#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
1032#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
1033#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
1035#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)
1037#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
1038#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
1039#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
1040#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
1041
1042/* Debug MCU registers base address */
1043#define DBGMCU_BASE 0xE0042000UL
1044
1046#define USB_OTG_HS_PERIPH_BASE 0x40040000UL
1047#define USB_OTG_FS_PERIPH_BASE 0x50000000UL
1048
1049#define USB_OTG_GLOBAL_BASE 0x0000UL
1050#define USB_OTG_DEVICE_BASE 0x0800UL
1051#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL
1052#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL
1053#define USB_OTG_EP_REG_SIZE 0x0020UL
1054#define USB_OTG_HOST_BASE 0x0400UL
1055#define USB_OTG_HOST_PORT_BASE 0x0440UL
1056#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL
1057#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL
1058#define USB_OTG_PCGCCTL_BASE 0x0E00UL
1059#define USB_OTG_FIFO_BASE 0x1000UL
1060#define USB_OTG_FIFO_SIZE 0x1000UL
1061
1069#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1070#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1071#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1072#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1073#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1074#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1075#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1076#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1077#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1078#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
1079#define RTC ((RTC_TypeDef *) RTC_BASE)
1080#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1081#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1082#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1083#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1084#define USART2 ((USART_TypeDef *) USART2_BASE)
1085#define USART3 ((USART_TypeDef *) USART3_BASE)
1086#define UART4 ((USART_TypeDef *) UART4_BASE)
1087#define UART5 ((USART_TypeDef *) UART5_BASE)
1088#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1089#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1090#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1091#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1092#define PWR ((PWR_TypeDef *) PWR_BASE)
1093#define DAC1 ((DAC_TypeDef *) DAC_BASE)
1094#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1095#define UART7 ((USART_TypeDef *) UART7_BASE)
1096#define UART8 ((USART_TypeDef *) UART8_BASE)
1097#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1098#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1099#define USART1 ((USART_TypeDef *) USART1_BASE)
1100#define USART6 ((USART_TypeDef *) USART6_BASE)
1101#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
1102#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1103#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1104#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1105#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
1106#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
1107#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1108#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1109#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1110#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1111#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1112#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1113#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1114#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1115#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1116#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
1117#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1118#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1119#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
1120#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
1121#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1122#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1123#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1124#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1125#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1126#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1127#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1128#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1129#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1130#define CRC ((CRC_TypeDef *) CRC_BASE)
1131#define RCC ((RCC_TypeDef *) RCC_BASE)
1132#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1133#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1134#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1135#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1136#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1137#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1138#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1139#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1140#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1141#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1142#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1143#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1144#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1145#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1146#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1147#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1148#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1149#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1150#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1151#define RNG ((RNG_TypeDef *) RNG_BASE)
1152#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1153#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1154#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1155#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1156#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1157#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1158#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1159#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1160#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
1161
1174/******************************************************************************/
1175/* Peripheral Registers_Bits_Definition */
1176/******************************************************************************/
1177
1178/******************************************************************************/
1179/* */
1180/* Analog to Digital Converter */
1181/* */
1182/******************************************************************************/
1183#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A))
1184#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF07A2C))
1185#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF07A2E))
1187/******************** Bit definition for ADC_SR register ********************/
1188#define ADC_SR_AWD_Pos (0U)
1189#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
1190#define ADC_SR_AWD ADC_SR_AWD_Msk
1191#define ADC_SR_EOC_Pos (1U)
1192#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos)
1193#define ADC_SR_EOC ADC_SR_EOC_Msk
1194#define ADC_SR_JEOC_Pos (2U)
1195#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos)
1196#define ADC_SR_JEOC ADC_SR_JEOC_Msk
1197#define ADC_SR_JSTRT_Pos (3U)
1198#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
1199#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
1200#define ADC_SR_STRT_Pos (4U)
1201#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
1202#define ADC_SR_STRT ADC_SR_STRT_Msk
1203#define ADC_SR_OVR_Pos (5U)
1204#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos)
1205#define ADC_SR_OVR ADC_SR_OVR_Msk
1207/******************* Bit definition for ADC_CR1 register ********************/
1208#define ADC_CR1_AWDCH_Pos (0U)
1209#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
1210#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
1211#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
1212#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
1213#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
1214#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
1215#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
1216#define ADC_CR1_EOCIE_Pos (5U)
1217#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos)
1218#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk
1219#define ADC_CR1_AWDIE_Pos (6U)
1220#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
1221#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
1222#define ADC_CR1_JEOCIE_Pos (7U)
1223#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos)
1224#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk
1225#define ADC_CR1_SCAN_Pos (8U)
1226#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
1227#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
1228#define ADC_CR1_AWDSGL_Pos (9U)
1229#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
1230#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
1231#define ADC_CR1_JAUTO_Pos (10U)
1232#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
1233#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
1234#define ADC_CR1_DISCEN_Pos (11U)
1235#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
1236#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
1237#define ADC_CR1_JDISCEN_Pos (12U)
1238#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
1239#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
1240#define ADC_CR1_DISCNUM_Pos (13U)
1241#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
1242#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
1243#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
1244#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
1245#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
1246#define ADC_CR1_JAWDEN_Pos (22U)
1247#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
1248#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
1249#define ADC_CR1_AWDEN_Pos (23U)
1250#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
1251#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
1252#define ADC_CR1_RES_Pos (24U)
1253#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos)
1254#define ADC_CR1_RES ADC_CR1_RES_Msk
1255#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos)
1256#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos)
1257#define ADC_CR1_OVRIE_Pos (26U)
1258#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos)
1259#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk
1261/******************* Bit definition for ADC_CR2 register ********************/
1262#define ADC_CR2_ADON_Pos (0U)
1263#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
1264#define ADC_CR2_ADON ADC_CR2_ADON_Msk
1265#define ADC_CR2_CONT_Pos (1U)
1266#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
1267#define ADC_CR2_CONT ADC_CR2_CONT_Msk
1268#define ADC_CR2_DMA_Pos (8U)
1269#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
1270#define ADC_CR2_DMA ADC_CR2_DMA_Msk
1271#define ADC_CR2_DDS_Pos (9U)
1272#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos)
1273#define ADC_CR2_DDS ADC_CR2_DDS_Msk
1274#define ADC_CR2_EOCS_Pos (10U)
1275#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos)
1276#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk
1277#define ADC_CR2_ALIGN_Pos (11U)
1278#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
1279#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
1280#define ADC_CR2_JEXTSEL_Pos (16U)
1281#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos)
1282#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
1283#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
1284#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
1285#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
1286#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos)
1287#define ADC_CR2_JEXTEN_Pos (20U)
1288#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos)
1289#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk
1290#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos)
1291#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos)
1292#define ADC_CR2_JSWSTART_Pos (22U)
1293#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
1294#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
1295#define ADC_CR2_EXTSEL_Pos (24U)
1296#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos)
1297#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
1298#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
1299#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
1300#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
1301#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos)
1302#define ADC_CR2_EXTEN_Pos (28U)
1303#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos)
1304#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk
1305#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos)
1306#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos)
1307#define ADC_CR2_SWSTART_Pos (30U)
1308#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
1309#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
1311/****************** Bit definition for ADC_SMPR1 register *******************/
1312#define ADC_SMPR1_SMP10_Pos (0U)
1313#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
1314#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
1315#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
1316#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
1317#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
1318#define ADC_SMPR1_SMP11_Pos (3U)
1319#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
1320#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
1321#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
1322#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
1323#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
1324#define ADC_SMPR1_SMP12_Pos (6U)
1325#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
1326#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
1327#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
1328#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
1329#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
1330#define ADC_SMPR1_SMP13_Pos (9U)
1331#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
1332#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
1333#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
1334#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
1335#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
1336#define ADC_SMPR1_SMP14_Pos (12U)
1337#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
1338#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
1339#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
1340#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
1341#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
1342#define ADC_SMPR1_SMP15_Pos (15U)
1343#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
1344#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
1345#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
1346#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
1347#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
1348#define ADC_SMPR1_SMP16_Pos (18U)
1349#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
1350#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
1351#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
1352#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
1353#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
1354#define ADC_SMPR1_SMP17_Pos (21U)
1355#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
1356#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
1357#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
1358#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
1359#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
1360#define ADC_SMPR1_SMP18_Pos (24U)
1361#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos)
1362#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk
1363#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos)
1364#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos)
1365#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos)
1367/****************** Bit definition for ADC_SMPR2 register *******************/
1368#define ADC_SMPR2_SMP0_Pos (0U)
1369#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
1370#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
1371#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
1372#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
1373#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
1374#define ADC_SMPR2_SMP1_Pos (3U)
1375#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
1376#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
1377#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
1378#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
1379#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
1380#define ADC_SMPR2_SMP2_Pos (6U)
1381#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
1382#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
1383#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
1384#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
1385#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
1386#define ADC_SMPR2_SMP3_Pos (9U)
1387#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
1388#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
1389#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
1390#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
1391#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
1392#define ADC_SMPR2_SMP4_Pos (12U)
1393#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
1394#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
1395#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
1396#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
1397#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
1398#define ADC_SMPR2_SMP5_Pos (15U)
1399#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
1400#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
1401#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
1402#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
1403#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
1404#define ADC_SMPR2_SMP6_Pos (18U)
1405#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
1406#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
1407#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
1408#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
1409#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
1410#define ADC_SMPR2_SMP7_Pos (21U)
1411#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
1412#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
1413#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
1414#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
1415#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
1416#define ADC_SMPR2_SMP8_Pos (24U)
1417#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
1418#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
1419#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
1420#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
1421#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
1422#define ADC_SMPR2_SMP9_Pos (27U)
1423#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
1424#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
1425#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
1426#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
1427#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
1429/****************** Bit definition for ADC_JOFR1 register *******************/
1430#define ADC_JOFR1_JOFFSET1_Pos (0U)
1431#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
1432#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
1434/****************** Bit definition for ADC_JOFR2 register *******************/
1435#define ADC_JOFR2_JOFFSET2_Pos (0U)
1436#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
1437#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
1439/****************** Bit definition for ADC_JOFR3 register *******************/
1440#define ADC_JOFR3_JOFFSET3_Pos (0U)
1441#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
1442#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
1444/****************** Bit definition for ADC_JOFR4 register *******************/
1445#define ADC_JOFR4_JOFFSET4_Pos (0U)
1446#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
1447#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
1449/******************* Bit definition for ADC_HTR register ********************/
1450#define ADC_HTR_HT_Pos (0U)
1451#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
1452#define ADC_HTR_HT ADC_HTR_HT_Msk
1454/******************* Bit definition for ADC_LTR register ********************/
1455#define ADC_LTR_LT_Pos (0U)
1456#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
1457#define ADC_LTR_LT ADC_LTR_LT_Msk
1459/******************* Bit definition for ADC_SQR1 register *******************/
1460#define ADC_SQR1_SQ13_Pos (0U)
1461#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
1462#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
1463#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
1464#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
1465#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
1466#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
1467#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
1468#define ADC_SQR1_SQ14_Pos (5U)
1469#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
1470#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
1471#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
1472#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
1473#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
1474#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
1475#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
1476#define ADC_SQR1_SQ15_Pos (10U)
1477#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
1478#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
1479#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
1480#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
1481#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
1482#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
1483#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
1484#define ADC_SQR1_SQ16_Pos (15U)
1485#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
1486#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
1487#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
1488#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
1489#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
1490#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
1491#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
1492#define ADC_SQR1_L_Pos (20U)
1493#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
1494#define ADC_SQR1_L ADC_SQR1_L_Msk
1495#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
1496#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
1497#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
1498#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
1500/******************* Bit definition for ADC_SQR2 register *******************/
1501#define ADC_SQR2_SQ7_Pos (0U)
1502#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
1503#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
1504#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
1505#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
1506#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
1507#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
1508#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
1509#define ADC_SQR2_SQ8_Pos (5U)
1510#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
1511#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
1512#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
1513#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
1514#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
1515#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
1516#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
1517#define ADC_SQR2_SQ9_Pos (10U)
1518#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
1519#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
1520#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
1521#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
1522#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
1523#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
1524#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
1525#define ADC_SQR2_SQ10_Pos (15U)
1526#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
1527#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
1528#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
1529#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
1530#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
1531#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
1532#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
1533#define ADC_SQR2_SQ11_Pos (20U)
1534#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
1535#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
1536#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
1537#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
1538#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
1539#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
1540#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
1541#define ADC_SQR2_SQ12_Pos (25U)
1542#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
1543#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
1544#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
1545#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
1546#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
1547#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
1548#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
1550/******************* Bit definition for ADC_SQR3 register *******************/
1551#define ADC_SQR3_SQ1_Pos (0U)
1552#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
1553#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
1554#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
1555#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
1556#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
1557#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
1558#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
1559#define ADC_SQR3_SQ2_Pos (5U)
1560#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
1561#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
1562#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
1563#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
1564#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
1565#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
1566#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
1567#define ADC_SQR3_SQ3_Pos (10U)
1568#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
1569#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
1570#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
1571#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
1572#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
1573#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
1574#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
1575#define ADC_SQR3_SQ4_Pos (15U)
1576#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
1577#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
1578#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
1579#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
1580#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
1581#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
1582#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
1583#define ADC_SQR3_SQ5_Pos (20U)
1584#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
1585#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
1586#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
1587#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
1588#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
1589#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
1590#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
1591#define ADC_SQR3_SQ6_Pos (25U)
1592#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
1593#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
1594#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
1595#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
1596#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
1597#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
1598#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
1600/******************* Bit definition for ADC_JSQR register *******************/
1601#define ADC_JSQR_JSQ1_Pos (0U)
1602#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
1603#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
1604#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
1605#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
1606#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
1607#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
1608#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
1609#define ADC_JSQR_JSQ2_Pos (5U)
1610#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
1611#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
1612#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
1613#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
1614#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
1615#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
1616#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
1617#define ADC_JSQR_JSQ3_Pos (10U)
1618#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
1619#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
1620#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
1621#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
1622#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
1623#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
1624#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
1625#define ADC_JSQR_JSQ4_Pos (15U)
1626#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
1627#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
1628#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
1629#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
1630#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
1631#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
1632#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
1633#define ADC_JSQR_JL_Pos (20U)
1634#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
1635#define ADC_JSQR_JL ADC_JSQR_JL_Msk
1636#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
1637#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
1639/******************* Bit definition for ADC_JDR1 register *******************/
1640#define ADC_JDR1_JDATA ((uint16_t)0xFFFFU)
1642/******************* Bit definition for ADC_JDR2 register *******************/
1643#define ADC_JDR2_JDATA ((uint16_t)0xFFFFU)
1645/******************* Bit definition for ADC_JDR3 register *******************/
1646#define ADC_JDR3_JDATA ((uint16_t)0xFFFFU)
1648/******************* Bit definition for ADC_JDR4 register *******************/
1649#define ADC_JDR4_JDATA ((uint16_t)0xFFFFU)
1651/******************** Bit definition for ADC_DR register ********************/
1652#define ADC_DR_DATA_Pos (0U)
1653#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
1654#define ADC_DR_DATA ADC_DR_DATA_Msk
1655#define ADC_DR_ADC2DATA_Pos (16U)
1656#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
1657#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
1659/******************* Bit definition for ADC_CSR register ********************/
1660#define ADC_CSR_AWD1_Pos (0U)
1661#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos)
1662#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk
1663#define ADC_CSR_EOC1_Pos (1U)
1664#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos)
1665#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk
1666#define ADC_CSR_JEOC1_Pos (2U)
1667#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos)
1668#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk
1669#define ADC_CSR_JSTRT1_Pos (3U)
1670#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos)
1671#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk
1672#define ADC_CSR_STRT1_Pos (4U)
1673#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos)
1674#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk
1675#define ADC_CSR_OVR1_Pos (5U)
1676#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos)
1677#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk
1678#define ADC_CSR_AWD2_Pos (8U)
1679#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos)
1680#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk
1681#define ADC_CSR_EOC2_Pos (9U)
1682#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos)
1683#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk
1684#define ADC_CSR_JEOC2_Pos (10U)
1685#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos)
1686#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk
1687#define ADC_CSR_JSTRT2_Pos (11U)
1688#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos)
1689#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk
1690#define ADC_CSR_STRT2_Pos (12U)
1691#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos)
1692#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk
1693#define ADC_CSR_OVR2_Pos (13U)
1694#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos)
1695#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk
1696#define ADC_CSR_AWD3_Pos (16U)
1697#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos)
1698#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk
1699#define ADC_CSR_EOC3_Pos (17U)
1700#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos)
1701#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk
1702#define ADC_CSR_JEOC3_Pos (18U)
1703#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos)
1704#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk
1705#define ADC_CSR_JSTRT3_Pos (19U)
1706#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos)
1707#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk
1708#define ADC_CSR_STRT3_Pos (20U)
1709#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos)
1710#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk
1711#define ADC_CSR_OVR3_Pos (21U)
1712#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos)
1713#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk
1715/* Legacy defines */
1716#define ADC_CSR_DOVR1 ADC_CSR_OVR1
1717#define ADC_CSR_DOVR2 ADC_CSR_OVR2
1718#define ADC_CSR_DOVR3 ADC_CSR_OVR3
1719
1720
1721/******************* Bit definition for ADC_CCR register ********************/
1722#define ADC_CCR_MULTI_Pos (0U)
1723#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos)
1724#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk
1725#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos)
1726#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos)
1727#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos)
1728#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos)
1729#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos)
1730#define ADC_CCR_DELAY_Pos (8U)
1731#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
1732#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
1733#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
1734#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
1735#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
1736#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
1737#define ADC_CCR_DDS_Pos (13U)
1738#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos)
1739#define ADC_CCR_DDS ADC_CCR_DDS_Msk
1740#define ADC_CCR_DMA_Pos (14U)
1741#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos)
1742#define ADC_CCR_DMA ADC_CCR_DMA_Msk
1743#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos)
1744#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos)
1745#define ADC_CCR_ADCPRE_Pos (16U)
1746#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos)
1747#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk
1748#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos)
1749#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos)
1750#define ADC_CCR_VBATE_Pos (22U)
1751#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos)
1752#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk
1753#define ADC_CCR_TSVREFE_Pos (23U)
1754#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos)
1755#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk
1757/******************* Bit definition for ADC_CDR register ********************/
1758#define ADC_CDR_DATA1_Pos (0U)
1759#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos)
1760#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk
1761#define ADC_CDR_DATA2_Pos (16U)
1762#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos)
1763#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk
1765/* Legacy defines */
1766#define ADC_CDR_RDATA_MST ADC_CDR_DATA1
1767#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
1768
1769/******************************************************************************/
1770/* */
1771/* Controller Area Network */
1772/* */
1773/******************************************************************************/
1775/******************* Bit definition for CAN_MCR register ********************/
1776#define CAN_MCR_INRQ_Pos (0U)
1777#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
1778#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
1779#define CAN_MCR_SLEEP_Pos (1U)
1780#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
1781#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
1782#define CAN_MCR_TXFP_Pos (2U)
1783#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
1784#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
1785#define CAN_MCR_RFLM_Pos (3U)
1786#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
1787#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
1788#define CAN_MCR_NART_Pos (4U)
1789#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
1790#define CAN_MCR_NART CAN_MCR_NART_Msk
1791#define CAN_MCR_AWUM_Pos (5U)
1792#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
1793#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
1794#define CAN_MCR_ABOM_Pos (6U)
1795#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
1796#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
1797#define CAN_MCR_TTCM_Pos (7U)
1798#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
1799#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
1800#define CAN_MCR_RESET_Pos (15U)
1801#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
1802#define CAN_MCR_RESET CAN_MCR_RESET_Msk
1804/******************* Bit definition for CAN_MSR register ********************/
1805#define CAN_MSR_INAK_Pos (0U)
1806#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
1807#define CAN_MSR_INAK CAN_MSR_INAK_Msk
1808#define CAN_MSR_SLAK_Pos (1U)
1809#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
1810#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
1811#define CAN_MSR_ERRI_Pos (2U)
1812#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
1813#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
1814#define CAN_MSR_WKUI_Pos (3U)
1815#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
1816#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
1817#define CAN_MSR_SLAKI_Pos (4U)
1818#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
1819#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
1820#define CAN_MSR_TXM_Pos (8U)
1821#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
1822#define CAN_MSR_TXM CAN_MSR_TXM_Msk
1823#define CAN_MSR_RXM_Pos (9U)
1824#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
1825#define CAN_MSR_RXM CAN_MSR_RXM_Msk
1826#define CAN_MSR_SAMP_Pos (10U)
1827#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
1828#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
1829#define CAN_MSR_RX_Pos (11U)
1830#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
1831#define CAN_MSR_RX CAN_MSR_RX_Msk
1833/******************* Bit definition for CAN_TSR register ********************/
1834#define CAN_TSR_RQCP0_Pos (0U)
1835#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
1836#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
1837#define CAN_TSR_TXOK0_Pos (1U)
1838#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
1839#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
1840#define CAN_TSR_ALST0_Pos (2U)
1841#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
1842#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
1843#define CAN_TSR_TERR0_Pos (3U)
1844#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
1845#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
1846#define CAN_TSR_ABRQ0_Pos (7U)
1847#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
1848#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
1849#define CAN_TSR_RQCP1_Pos (8U)
1850#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
1851#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
1852#define CAN_TSR_TXOK1_Pos (9U)
1853#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
1854#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
1855#define CAN_TSR_ALST1_Pos (10U)
1856#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
1857#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
1858#define CAN_TSR_TERR1_Pos (11U)
1859#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
1860#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
1861#define CAN_TSR_ABRQ1_Pos (15U)
1862#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
1863#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
1864#define CAN_TSR_RQCP2_Pos (16U)
1865#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
1866#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
1867#define CAN_TSR_TXOK2_Pos (17U)
1868#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
1869#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
1870#define CAN_TSR_ALST2_Pos (18U)
1871#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
1872#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
1873#define CAN_TSR_TERR2_Pos (19U)
1874#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
1875#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
1876#define CAN_TSR_ABRQ2_Pos (23U)
1877#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
1878#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
1879#define CAN_TSR_CODE_Pos (24U)
1880#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
1881#define CAN_TSR_CODE CAN_TSR_CODE_Msk
1883#define CAN_TSR_TME_Pos (26U)
1884#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
1885#define CAN_TSR_TME CAN_TSR_TME_Msk
1886#define CAN_TSR_TME0_Pos (26U)
1887#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
1888#define CAN_TSR_TME0 CAN_TSR_TME0_Msk
1889#define CAN_TSR_TME1_Pos (27U)
1890#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
1891#define CAN_TSR_TME1 CAN_TSR_TME1_Msk
1892#define CAN_TSR_TME2_Pos (28U)
1893#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
1894#define CAN_TSR_TME2 CAN_TSR_TME2_Msk
1896#define CAN_TSR_LOW_Pos (29U)
1897#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
1898#define CAN_TSR_LOW CAN_TSR_LOW_Msk
1899#define CAN_TSR_LOW0_Pos (29U)
1900#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
1901#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
1902#define CAN_TSR_LOW1_Pos (30U)
1903#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
1904#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
1905#define CAN_TSR_LOW2_Pos (31U)
1906#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
1907#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
1909/******************* Bit definition for CAN_RF0R register *******************/
1910#define CAN_RF0R_FMP0_Pos (0U)
1911#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
1912#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
1913#define CAN_RF0R_FULL0_Pos (3U)
1914#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
1915#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
1916#define CAN_RF0R_FOVR0_Pos (4U)
1917#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
1918#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
1919#define CAN_RF0R_RFOM0_Pos (5U)
1920#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
1921#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
1923/******************* Bit definition for CAN_RF1R register *******************/
1924#define CAN_RF1R_FMP1_Pos (0U)
1925#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
1926#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
1927#define CAN_RF1R_FULL1_Pos (3U)
1928#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
1929#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
1930#define CAN_RF1R_FOVR1_Pos (4U)
1931#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
1932#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
1933#define CAN_RF1R_RFOM1_Pos (5U)
1934#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
1935#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
1937/******************** Bit definition for CAN_IER register *******************/
1938#define CAN_IER_TMEIE_Pos (0U)
1939#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
1940#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
1941#define CAN_IER_FMPIE0_Pos (1U)
1942#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
1943#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
1944#define CAN_IER_FFIE0_Pos (2U)
1945#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
1946#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
1947#define CAN_IER_FOVIE0_Pos (3U)
1948#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
1949#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
1950#define CAN_IER_FMPIE1_Pos (4U)
1951#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
1952#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
1953#define CAN_IER_FFIE1_Pos (5U)
1954#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
1955#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
1956#define CAN_IER_FOVIE1_Pos (6U)
1957#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
1958#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
1959#define CAN_IER_EWGIE_Pos (8U)
1960#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
1961#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
1962#define CAN_IER_EPVIE_Pos (9U)
1963#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
1964#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
1965#define CAN_IER_BOFIE_Pos (10U)
1966#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
1967#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
1968#define CAN_IER_LECIE_Pos (11U)
1969#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
1970#define CAN_IER_LECIE CAN_IER_LECIE_Msk
1971#define CAN_IER_ERRIE_Pos (15U)
1972#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
1973#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
1974#define CAN_IER_WKUIE_Pos (16U)
1975#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
1976#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
1977#define CAN_IER_SLKIE_Pos (17U)
1978#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
1979#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
1981/******************** Bit definition for CAN_ESR register *******************/
1982#define CAN_ESR_EWGF_Pos (0U)
1983#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
1984#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
1985#define CAN_ESR_EPVF_Pos (1U)
1986#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
1987#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
1988#define CAN_ESR_BOFF_Pos (2U)
1989#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
1990#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
1992#define CAN_ESR_LEC_Pos (4U)
1993#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
1994#define CAN_ESR_LEC CAN_ESR_LEC_Msk
1995#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
1996#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
1997#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
1999#define CAN_ESR_TEC_Pos (16U)
2000#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
2001#define CAN_ESR_TEC CAN_ESR_TEC_Msk
2002#define CAN_ESR_REC_Pos (24U)
2003#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
2004#define CAN_ESR_REC CAN_ESR_REC_Msk
2006/******************* Bit definition for CAN_BTR register ********************/
2007#define CAN_BTR_BRP_Pos (0U)
2008#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
2009#define CAN_BTR_BRP CAN_BTR_BRP_Msk
2010#define CAN_BTR_TS1_Pos (16U)
2011#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
2012#define CAN_BTR_TS1 CAN_BTR_TS1_Msk
2013#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
2014#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
2015#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
2016#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
2017#define CAN_BTR_TS2_Pos (20U)
2018#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
2019#define CAN_BTR_TS2 CAN_BTR_TS2_Msk
2020#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
2021#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
2022#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
2023#define CAN_BTR_SJW_Pos (24U)
2024#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
2025#define CAN_BTR_SJW CAN_BTR_SJW_Msk
2026#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
2027#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
2028#define CAN_BTR_LBKM_Pos (30U)
2029#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
2030#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
2031#define CAN_BTR_SILM_Pos (31U)
2032#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
2033#define CAN_BTR_SILM CAN_BTR_SILM_Msk
2036/****************** Bit definition for CAN_TI0R register ********************/
2037#define CAN_TI0R_TXRQ_Pos (0U)
2038#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
2039#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
2040#define CAN_TI0R_RTR_Pos (1U)
2041#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
2042#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
2043#define CAN_TI0R_IDE_Pos (2U)
2044#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
2045#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
2046#define CAN_TI0R_EXID_Pos (3U)
2047#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
2048#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
2049#define CAN_TI0R_STID_Pos (21U)
2050#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
2051#define CAN_TI0R_STID CAN_TI0R_STID_Msk
2053/****************** Bit definition for CAN_TDT0R register *******************/
2054#define CAN_TDT0R_DLC_Pos (0U)
2055#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
2056#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
2057#define CAN_TDT0R_TGT_Pos (8U)
2058#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
2059#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
2060#define CAN_TDT0R_TIME_Pos (16U)
2061#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
2062#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
2064/****************** Bit definition for CAN_TDL0R register *******************/
2065#define CAN_TDL0R_DATA0_Pos (0U)
2066#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
2067#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
2068#define CAN_TDL0R_DATA1_Pos (8U)
2069#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
2070#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
2071#define CAN_TDL0R_DATA2_Pos (16U)
2072#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
2073#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
2074#define CAN_TDL0R_DATA3_Pos (24U)
2075#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
2076#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
2078/****************** Bit definition for CAN_TDH0R register *******************/
2079#define CAN_TDH0R_DATA4_Pos (0U)
2080#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
2081#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
2082#define CAN_TDH0R_DATA5_Pos (8U)
2083#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
2084#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
2085#define CAN_TDH0R_DATA6_Pos (16U)
2086#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
2087#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
2088#define CAN_TDH0R_DATA7_Pos (24U)
2089#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
2090#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
2092/******************* Bit definition for CAN_TI1R register *******************/
2093#define CAN_TI1R_TXRQ_Pos (0U)
2094#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
2095#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
2096#define CAN_TI1R_RTR_Pos (1U)
2097#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
2098#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
2099#define CAN_TI1R_IDE_Pos (2U)
2100#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
2101#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
2102#define CAN_TI1R_EXID_Pos (3U)
2103#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
2104#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
2105#define CAN_TI1R_STID_Pos (21U)
2106#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
2107#define CAN_TI1R_STID CAN_TI1R_STID_Msk
2109/******************* Bit definition for CAN_TDT1R register ******************/
2110#define CAN_TDT1R_DLC_Pos (0U)
2111#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
2112#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
2113#define CAN_TDT1R_TGT_Pos (8U)
2114#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
2115#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
2116#define CAN_TDT1R_TIME_Pos (16U)
2117#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
2118#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
2120/******************* Bit definition for CAN_TDL1R register ******************/
2121#define CAN_TDL1R_DATA0_Pos (0U)
2122#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
2123#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
2124#define CAN_TDL1R_DATA1_Pos (8U)
2125#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
2126#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
2127#define CAN_TDL1R_DATA2_Pos (16U)
2128#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
2129#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
2130#define CAN_TDL1R_DATA3_Pos (24U)
2131#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
2132#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
2134/******************* Bit definition for CAN_TDH1R register ******************/
2135#define CAN_TDH1R_DATA4_Pos (0U)
2136#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
2137#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
2138#define CAN_TDH1R_DATA5_Pos (8U)
2139#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
2140#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
2141#define CAN_TDH1R_DATA6_Pos (16U)
2142#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
2143#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
2144#define CAN_TDH1R_DATA7_Pos (24U)
2145#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
2146#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
2148/******************* Bit definition for CAN_TI2R register *******************/
2149#define CAN_TI2R_TXRQ_Pos (0U)
2150#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
2151#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
2152#define CAN_TI2R_RTR_Pos (1U)
2153#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
2154#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
2155#define CAN_TI2R_IDE_Pos (2U)
2156#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
2157#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
2158#define CAN_TI2R_EXID_Pos (3U)
2159#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
2160#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
2161#define CAN_TI2R_STID_Pos (21U)
2162#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
2163#define CAN_TI2R_STID CAN_TI2R_STID_Msk
2165/******************* Bit definition for CAN_TDT2R register ******************/
2166#define CAN_TDT2R_DLC_Pos (0U)
2167#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
2168#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
2169#define CAN_TDT2R_TGT_Pos (8U)
2170#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
2171#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
2172#define CAN_TDT2R_TIME_Pos (16U)
2173#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
2174#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
2176/******************* Bit definition for CAN_TDL2R register ******************/
2177#define CAN_TDL2R_DATA0_Pos (0U)
2178#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
2179#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
2180#define CAN_TDL2R_DATA1_Pos (8U)
2181#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
2182#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
2183#define CAN_TDL2R_DATA2_Pos (16U)
2184#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
2185#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
2186#define CAN_TDL2R_DATA3_Pos (24U)
2187#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
2188#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
2190/******************* Bit definition for CAN_TDH2R register ******************/
2191#define CAN_TDH2R_DATA4_Pos (0U)
2192#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
2193#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
2194#define CAN_TDH2R_DATA5_Pos (8U)
2195#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
2196#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
2197#define CAN_TDH2R_DATA6_Pos (16U)
2198#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
2199#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
2200#define CAN_TDH2R_DATA7_Pos (24U)
2201#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
2202#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
2204/******************* Bit definition for CAN_RI0R register *******************/
2205#define CAN_RI0R_RTR_Pos (1U)
2206#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
2207#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
2208#define CAN_RI0R_IDE_Pos (2U)
2209#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
2210#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
2211#define CAN_RI0R_EXID_Pos (3U)
2212#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
2213#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
2214#define CAN_RI0R_STID_Pos (21U)
2215#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
2216#define CAN_RI0R_STID CAN_RI0R_STID_Msk
2218/******************* Bit definition for CAN_RDT0R register ******************/
2219#define CAN_RDT0R_DLC_Pos (0U)
2220#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
2221#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
2222#define CAN_RDT0R_FMI_Pos (8U)
2223#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
2224#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
2225#define CAN_RDT0R_TIME_Pos (16U)
2226#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
2227#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
2229/******************* Bit definition for CAN_RDL0R register ******************/
2230#define CAN_RDL0R_DATA0_Pos (0U)
2231#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
2232#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
2233#define CAN_RDL0R_DATA1_Pos (8U)
2234#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
2235#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
2236#define CAN_RDL0R_DATA2_Pos (16U)
2237#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
2238#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
2239#define CAN_RDL0R_DATA3_Pos (24U)
2240#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
2241#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
2243/******************* Bit definition for CAN_RDH0R register ******************/
2244#define CAN_RDH0R_DATA4_Pos (0U)
2245#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
2246#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
2247#define CAN_RDH0R_DATA5_Pos (8U)
2248#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
2249#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
2250#define CAN_RDH0R_DATA6_Pos (16U)
2251#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
2252#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
2253#define CAN_RDH0R_DATA7_Pos (24U)
2254#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
2255#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
2257/******************* Bit definition for CAN_RI1R register *******************/
2258#define CAN_RI1R_RTR_Pos (1U)
2259#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
2260#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
2261#define CAN_RI1R_IDE_Pos (2U)
2262#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
2263#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
2264#define CAN_RI1R_EXID_Pos (3U)
2265#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
2266#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
2267#define CAN_RI1R_STID_Pos (21U)
2268#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
2269#define CAN_RI1R_STID CAN_RI1R_STID_Msk
2271/******************* Bit definition for CAN_RDT1R register ******************/
2272#define CAN_RDT1R_DLC_Pos (0U)
2273#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
2274#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
2275#define CAN_RDT1R_FMI_Pos (8U)
2276#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
2277#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
2278#define CAN_RDT1R_TIME_Pos (16U)
2279#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
2280#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
2282/******************* Bit definition for CAN_RDL1R register ******************/
2283#define CAN_RDL1R_DATA0_Pos (0U)
2284#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
2285#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
2286#define CAN_RDL1R_DATA1_Pos (8U)
2287#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
2288#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
2289#define CAN_RDL1R_DATA2_Pos (16U)
2290#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
2291#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
2292#define CAN_RDL1R_DATA3_Pos (24U)
2293#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
2294#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
2296/******************* Bit definition for CAN_RDH1R register ******************/
2297#define CAN_RDH1R_DATA4_Pos (0U)
2298#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
2299#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
2300#define CAN_RDH1R_DATA5_Pos (8U)
2301#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
2302#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
2303#define CAN_RDH1R_DATA6_Pos (16U)
2304#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
2305#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
2306#define CAN_RDH1R_DATA7_Pos (24U)
2307#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
2308#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
2311/******************* Bit definition for CAN_FMR register ********************/
2312#define CAN_FMR_FINIT ((uint8_t)0x01U)
2314/******************* Bit definition for CAN_FM1R register *******************/
2315#define CAN_FM1R_FBM_Pos (0U)
2316#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)
2317#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
2318#define CAN_FM1R_FBM0_Pos (0U)
2319#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
2320#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
2321#define CAN_FM1R_FBM1_Pos (1U)
2322#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
2323#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
2324#define CAN_FM1R_FBM2_Pos (2U)
2325#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
2326#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
2327#define CAN_FM1R_FBM3_Pos (3U)
2328#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
2329#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
2330#define CAN_FM1R_FBM4_Pos (4U)
2331#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
2332#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
2333#define CAN_FM1R_FBM5_Pos (5U)
2334#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
2335#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
2336#define CAN_FM1R_FBM6_Pos (6U)
2337#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
2338#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
2339#define CAN_FM1R_FBM7_Pos (7U)
2340#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
2341#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
2342#define CAN_FM1R_FBM8_Pos (8U)
2343#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
2344#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
2345#define CAN_FM1R_FBM9_Pos (9U)
2346#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
2347#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
2348#define CAN_FM1R_FBM10_Pos (10U)
2349#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
2350#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
2351#define CAN_FM1R_FBM11_Pos (11U)
2352#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
2353#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
2354#define CAN_FM1R_FBM12_Pos (12U)
2355#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
2356#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
2357#define CAN_FM1R_FBM13_Pos (13U)
2358#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
2359#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
2361/******************* Bit definition for CAN_FS1R register *******************/
2362#define CAN_FS1R_FSC_Pos (0U)
2363#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)
2364#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
2365#define CAN_FS1R_FSC0_Pos (0U)
2366#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
2367#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
2368#define CAN_FS1R_FSC1_Pos (1U)
2369#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
2370#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
2371#define CAN_FS1R_FSC2_Pos (2U)
2372#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
2373#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
2374#define CAN_FS1R_FSC3_Pos (3U)
2375#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
2376#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
2377#define CAN_FS1R_FSC4_Pos (4U)
2378#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
2379#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
2380#define CAN_FS1R_FSC5_Pos (5U)
2381#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
2382#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
2383#define CAN_FS1R_FSC6_Pos (6U)
2384#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
2385#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
2386#define CAN_FS1R_FSC7_Pos (7U)
2387#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
2388#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
2389#define CAN_FS1R_FSC8_Pos (8U)
2390#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
2391#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
2392#define CAN_FS1R_FSC9_Pos (9U)
2393#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
2394#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
2395#define CAN_FS1R_FSC10_Pos (10U)
2396#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
2397#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
2398#define CAN_FS1R_FSC11_Pos (11U)
2399#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
2400#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
2401#define CAN_FS1R_FSC12_Pos (12U)
2402#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
2403#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
2404#define CAN_FS1R_FSC13_Pos (13U)
2405#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
2406#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
2408/****************** Bit definition for CAN_FFA1R register *******************/
2409#define CAN_FFA1R_FFA_Pos (0U)
2410#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)
2411#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
2412#define CAN_FFA1R_FFA0_Pos (0U)
2413#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
2414#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
2415#define CAN_FFA1R_FFA1_Pos (1U)
2416#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
2417#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
2418#define CAN_FFA1R_FFA2_Pos (2U)
2419#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
2420#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
2421#define CAN_FFA1R_FFA3_Pos (3U)
2422#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
2423#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
2424#define CAN_FFA1R_FFA4_Pos (4U)
2425#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
2426#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
2427#define CAN_FFA1R_FFA5_Pos (5U)
2428#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
2429#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
2430#define CAN_FFA1R_FFA6_Pos (6U)
2431#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
2432#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
2433#define CAN_FFA1R_FFA7_Pos (7U)
2434#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
2435#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
2436#define CAN_FFA1R_FFA8_Pos (8U)
2437#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
2438#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
2439#define CAN_FFA1R_FFA9_Pos (9U)
2440#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
2441#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
2442#define CAN_FFA1R_FFA10_Pos (10U)
2443#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
2444#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
2445#define CAN_FFA1R_FFA11_Pos (11U)
2446#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
2447#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
2448#define CAN_FFA1R_FFA12_Pos (12U)
2449#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
2450#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
2451#define CAN_FFA1R_FFA13_Pos (13U)
2452#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
2453#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
2455/******************* Bit definition for CAN_FA1R register *******************/
2456#define CAN_FA1R_FACT_Pos (0U)
2457#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)
2458#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
2459#define CAN_FA1R_FACT0_Pos (0U)
2460#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
2461#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
2462#define CAN_FA1R_FACT1_Pos (1U)
2463#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
2464#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
2465#define CAN_FA1R_FACT2_Pos (2U)
2466#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
2467#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
2468#define CAN_FA1R_FACT3_Pos (3U)
2469#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
2470#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
2471#define CAN_FA1R_FACT4_Pos (4U)
2472#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
2473#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
2474#define CAN_FA1R_FACT5_Pos (5U)
2475#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
2476#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
2477#define CAN_FA1R_FACT6_Pos (6U)
2478#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
2479#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
2480#define CAN_FA1R_FACT7_Pos (7U)
2481#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
2482#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
2483#define CAN_FA1R_FACT8_Pos (8U)
2484#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
2485#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
2486#define CAN_FA1R_FACT9_Pos (9U)
2487#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
2488#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
2489#define CAN_FA1R_FACT10_Pos (10U)
2490#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
2491#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
2492#define CAN_FA1R_FACT11_Pos (11U)
2493#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
2494#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
2495#define CAN_FA1R_FACT12_Pos (12U)
2496#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
2497#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
2498#define CAN_FA1R_FACT13_Pos (13U)
2499#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
2500#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
2502/******************* Bit definition for CAN_F0R1 register *******************/
2503#define CAN_F0R1_FB0_Pos (0U)
2504#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
2505#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
2506#define CAN_F0R1_FB1_Pos (1U)
2507#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
2508#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
2509#define CAN_F0R1_FB2_Pos (2U)
2510#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
2511#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
2512#define CAN_F0R1_FB3_Pos (3U)
2513#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
2514#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
2515#define CAN_F0R1_FB4_Pos (4U)
2516#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
2517#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
2518#define CAN_F0R1_FB5_Pos (5U)
2519#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
2520#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
2521#define CAN_F0R1_FB6_Pos (6U)
2522#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
2523#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
2524#define CAN_F0R1_FB7_Pos (7U)
2525#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
2526#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
2527#define CAN_F0R1_FB8_Pos (8U)
2528#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
2529#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
2530#define CAN_F0R1_FB9_Pos (9U)
2531#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
2532#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
2533#define CAN_F0R1_FB10_Pos (10U)
2534#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
2535#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
2536#define CAN_F0R1_FB11_Pos (11U)
2537#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
2538#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
2539#define CAN_F0R1_FB12_Pos (12U)
2540#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
2541#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
2542#define CAN_F0R1_FB13_Pos (13U)
2543#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
2544#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
2545#define CAN_F0R1_FB14_Pos (14U)
2546#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
2547#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
2548#define CAN_F0R1_FB15_Pos (15U)
2549#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
2550#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
2551#define CAN_F0R1_FB16_Pos (16U)
2552#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
2553#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
2554#define CAN_F0R1_FB17_Pos (17U)
2555#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
2556#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
2557#define CAN_F0R1_FB18_Pos (18U)
2558#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
2559#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
2560#define CAN_F0R1_FB19_Pos (19U)
2561#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
2562#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
2563#define CAN_F0R1_FB20_Pos (20U)
2564#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
2565#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
2566#define CAN_F0R1_FB21_Pos (21U)
2567#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
2568#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
2569#define CAN_F0R1_FB22_Pos (22U)
2570#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
2571#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
2572#define CAN_F0R1_FB23_Pos (23U)
2573#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
2574#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
2575#define CAN_F0R1_FB24_Pos (24U)
2576#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
2577#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
2578#define CAN_F0R1_FB25_Pos (25U)
2579#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
2580#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
2581#define CAN_F0R1_FB26_Pos (26U)
2582#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
2583#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
2584#define CAN_F0R1_FB27_Pos (27U)
2585#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
2586#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
2587#define CAN_F0R1_FB28_Pos (28U)
2588#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
2589#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
2590#define CAN_F0R1_FB29_Pos (29U)
2591#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
2592#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
2593#define CAN_F0R1_FB30_Pos (30U)
2594#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
2595#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
2596#define CAN_F0R1_FB31_Pos (31U)
2597#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
2598#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
2600/******************* Bit definition for CAN_F1R1 register *******************/
2601#define CAN_F1R1_FB0_Pos (0U)
2602#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
2603#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
2604#define CAN_F1R1_FB1_Pos (1U)
2605#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
2606#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
2607#define CAN_F1R1_FB2_Pos (2U)
2608#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
2609#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
2610#define CAN_F1R1_FB3_Pos (3U)
2611#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
2612#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
2613#define CAN_F1R1_FB4_Pos (4U)
2614#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
2615#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
2616#define CAN_F1R1_FB5_Pos (5U)
2617#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
2618#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
2619#define CAN_F1R1_FB6_Pos (6U)
2620#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
2621#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
2622#define CAN_F1R1_FB7_Pos (7U)
2623#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
2624#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
2625#define CAN_F1R1_FB8_Pos (8U)
2626#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
2627#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
2628#define CAN_F1R1_FB9_Pos (9U)
2629#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
2630#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
2631#define CAN_F1R1_FB10_Pos (10U)
2632#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
2633#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
2634#define CAN_F1R1_FB11_Pos (11U)
2635#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
2636#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
2637#define CAN_F1R1_FB12_Pos (12U)
2638#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
2639#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
2640#define CAN_F1R1_FB13_Pos (13U)
2641#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
2642#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
2643#define CAN_F1R1_FB14_Pos (14U)
2644#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
2645#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
2646#define CAN_F1R1_FB15_Pos (15U)
2647#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
2648#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
2649#define CAN_F1R1_FB16_Pos (16U)
2650#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
2651#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
2652#define CAN_F1R1_FB17_Pos (17U)
2653#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
2654#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
2655#define CAN_F1R1_FB18_Pos (18U)
2656#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
2657#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
2658#define CAN_F1R1_FB19_Pos (19U)
2659#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
2660#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
2661#define CAN_F1R1_FB20_Pos (20U)
2662#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
2663#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
2664#define CAN_F1R1_FB21_Pos (21U)
2665#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
2666#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
2667#define CAN_F1R1_FB22_Pos (22U)
2668#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
2669#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
2670#define CAN_F1R1_FB23_Pos (23U)
2671#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
2672#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
2673#define CAN_F1R1_FB24_Pos (24U)
2674#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
2675#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
2676#define CAN_F1R1_FB25_Pos (25U)
2677#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
2678#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
2679#define CAN_F1R1_FB26_Pos (26U)
2680#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
2681#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
2682#define CAN_F1R1_FB27_Pos (27U)
2683#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
2684#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
2685#define CAN_F1R1_FB28_Pos (28U)
2686#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
2687#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
2688#define CAN_F1R1_FB29_Pos (29U)
2689#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
2690#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
2691#define CAN_F1R1_FB30_Pos (30U)
2692#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
2693#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
2694#define CAN_F1R1_FB31_Pos (31U)
2695#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
2696#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
2698/******************* Bit definition for CAN_F2R1 register *******************/
2699#define CAN_F2R1_FB0_Pos (0U)
2700#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
2701#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
2702#define CAN_F2R1_FB1_Pos (1U)
2703#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
2704#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
2705#define CAN_F2R1_FB2_Pos (2U)
2706#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
2707#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
2708#define CAN_F2R1_FB3_Pos (3U)
2709#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
2710#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
2711#define CAN_F2R1_FB4_Pos (4U)
2712#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
2713#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
2714#define CAN_F2R1_FB5_Pos (5U)
2715#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
2716#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
2717#define CAN_F2R1_FB6_Pos (6U)
2718#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
2719#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
2720#define CAN_F2R1_FB7_Pos (7U)
2721#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
2722#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
2723#define CAN_F2R1_FB8_Pos (8U)
2724#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
2725#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
2726#define CAN_F2R1_FB9_Pos (9U)
2727#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
2728#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
2729#define CAN_F2R1_FB10_Pos (10U)
2730#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
2731#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
2732#define CAN_F2R1_FB11_Pos (11U)
2733#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
2734#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
2735#define CAN_F2R1_FB12_Pos (12U)
2736#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
2737#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
2738#define CAN_F2R1_FB13_Pos (13U)
2739#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
2740#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
2741#define CAN_F2R1_FB14_Pos (14U)
2742#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
2743#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
2744#define CAN_F2R1_FB15_Pos (15U)
2745#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
2746#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
2747#define CAN_F2R1_FB16_Pos (16U)
2748#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
2749#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
2750#define CAN_F2R1_FB17_Pos (17U)
2751#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
2752#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
2753#define CAN_F2R1_FB18_Pos (18U)
2754#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
2755#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
2756#define CAN_F2R1_FB19_Pos (19U)
2757#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
2758#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
2759#define CAN_F2R1_FB20_Pos (20U)
2760#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
2761#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
2762#define CAN_F2R1_FB21_Pos (21U)
2763#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
2764#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
2765#define CAN_F2R1_FB22_Pos (22U)
2766#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
2767#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
2768#define CAN_F2R1_FB23_Pos (23U)
2769#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
2770#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
2771#define CAN_F2R1_FB24_Pos (24U)
2772#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
2773#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
2774#define CAN_F2R1_FB25_Pos (25U)
2775#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
2776#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
2777#define CAN_F2R1_FB26_Pos (26U)
2778#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
2779#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
2780#define CAN_F2R1_FB27_Pos (27U)
2781#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
2782#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
2783#define CAN_F2R1_FB28_Pos (28U)
2784#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
2785#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
2786#define CAN_F2R1_FB29_Pos (29U)
2787#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
2788#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
2789#define CAN_F2R1_FB30_Pos (30U)
2790#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
2791#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
2792#define CAN_F2R1_FB31_Pos (31U)
2793#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
2794#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
2796/******************* Bit definition for CAN_F3R1 register *******************/
2797#define CAN_F3R1_FB0_Pos (0U)
2798#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
2799#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
2800#define CAN_F3R1_FB1_Pos (1U)
2801#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
2802#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
2803#define CAN_F3R1_FB2_Pos (2U)
2804#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
2805#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
2806#define CAN_F3R1_FB3_Pos (3U)
2807#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
2808#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
2809#define CAN_F3R1_FB4_Pos (4U)
2810#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
2811#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
2812#define CAN_F3R1_FB5_Pos (5U)
2813#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
2814#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
2815#define CAN_F3R1_FB6_Pos (6U)
2816#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
2817#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
2818#define CAN_F3R1_FB7_Pos (7U)
2819#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
2820#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
2821#define CAN_F3R1_FB8_Pos (8U)
2822#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
2823#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
2824#define CAN_F3R1_FB9_Pos (9U)
2825#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
2826#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
2827#define CAN_F3R1_FB10_Pos (10U)
2828#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
2829#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
2830#define CAN_F3R1_FB11_Pos (11U)
2831#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
2832#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
2833#define CAN_F3R1_FB12_Pos (12U)
2834#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
2835#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
2836#define CAN_F3R1_FB13_Pos (13U)
2837#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
2838#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
2839#define CAN_F3R1_FB14_Pos (14U)
2840#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
2841#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
2842#define CAN_F3R1_FB15_Pos (15U)
2843#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
2844#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
2845#define CAN_F3R1_FB16_Pos (16U)
2846#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
2847#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
2848#define CAN_F3R1_FB17_Pos (17U)
2849#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
2850#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
2851#define CAN_F3R1_FB18_Pos (18U)
2852#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
2853#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
2854#define CAN_F3R1_FB19_Pos (19U)
2855#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
2856#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
2857#define CAN_F3R1_FB20_Pos (20U)
2858#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
2859#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
2860#define CAN_F3R1_FB21_Pos (21U)
2861#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
2862#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
2863#define CAN_F3R1_FB22_Pos (22U)
2864#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
2865#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
2866#define CAN_F3R1_FB23_Pos (23U)
2867#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
2868#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
2869#define CAN_F3R1_FB24_Pos (24U)
2870#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
2871#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
2872#define CAN_F3R1_FB25_Pos (25U)
2873#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
2874#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
2875#define CAN_F3R1_FB26_Pos (26U)
2876#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
2877#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
2878#define CAN_F3R1_FB27_Pos (27U)
2879#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
2880#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
2881#define CAN_F3R1_FB28_Pos (28U)
2882#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
2883#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
2884#define CAN_F3R1_FB29_Pos (29U)
2885#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
2886#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
2887#define CAN_F3R1_FB30_Pos (30U)
2888#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
2889#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
2890#define CAN_F3R1_FB31_Pos (31U)
2891#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
2892#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
2894/******************* Bit definition for CAN_F4R1 register *******************/
2895#define CAN_F4R1_FB0_Pos (0U)
2896#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
2897#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
2898#define CAN_F4R1_FB1_Pos (1U)
2899#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
2900#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
2901#define CAN_F4R1_FB2_Pos (2U)
2902#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
2903#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
2904#define CAN_F4R1_FB3_Pos (3U)
2905#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
2906#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
2907#define CAN_F4R1_FB4_Pos (4U)
2908#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
2909#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
2910#define CAN_F4R1_FB5_Pos (5U)
2911#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
2912#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
2913#define CAN_F4R1_FB6_Pos (6U)
2914#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
2915#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
2916#define CAN_F4R1_FB7_Pos (7U)
2917#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
2918#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
2919#define CAN_F4R1_FB8_Pos (8U)
2920#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
2921#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
2922#define CAN_F4R1_FB9_Pos (9U)
2923#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
2924#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
2925#define CAN_F4R1_FB10_Pos (10U)
2926#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
2927#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
2928#define CAN_F4R1_FB11_Pos (11U)
2929#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
2930#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
2931#define CAN_F4R1_FB12_Pos (12U)
2932#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
2933#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
2934#define CAN_F4R1_FB13_Pos (13U)
2935#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
2936#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
2937#define CAN_F4R1_FB14_Pos (14U)
2938#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
2939#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
2940#define CAN_F4R1_FB15_Pos (15U)
2941#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
2942#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
2943#define CAN_F4R1_FB16_Pos (16U)
2944#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
2945#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
2946#define CAN_F4R1_FB17_Pos (17U)
2947#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
2948#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
2949#define CAN_F4R1_FB18_Pos (18U)
2950#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
2951#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
2952#define CAN_F4R1_FB19_Pos (19U)
2953#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
2954#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
2955#define CAN_F4R1_FB20_Pos (20U)
2956#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
2957#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
2958#define CAN_F4R1_FB21_Pos (21U)
2959#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
2960#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
2961#define CAN_F4R1_FB22_Pos (22U)
2962#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
2963#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
2964#define CAN_F4R1_FB23_Pos (23U)
2965#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
2966#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
2967#define CAN_F4R1_FB24_Pos (24U)
2968#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
2969#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
2970#define CAN_F4R1_FB25_Pos (25U)
2971#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
2972#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
2973#define CAN_F4R1_FB26_Pos (26U)
2974#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
2975#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
2976#define CAN_F4R1_FB27_Pos (27U)
2977#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
2978#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
2979#define CAN_F4R1_FB28_Pos (28U)
2980#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
2981#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
2982#define CAN_F4R1_FB29_Pos (29U)
2983#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
2984#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
2985#define CAN_F4R1_FB30_Pos (30U)
2986#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
2987#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
2988#define CAN_F4R1_FB31_Pos (31U)
2989#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
2990#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
2992/******************* Bit definition for CAN_F5R1 register *******************/
2993#define CAN_F5R1_FB0_Pos (0U)
2994#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
2995#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
2996#define CAN_F5R1_FB1_Pos (1U)
2997#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
2998#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
2999#define CAN_F5R1_FB2_Pos (2U)
3000#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
3001#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
3002#define CAN_F5R1_FB3_Pos (3U)
3003#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
3004#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
3005#define CAN_F5R1_FB4_Pos (4U)
3006#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
3007#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
3008#define CAN_F5R1_FB5_Pos (5U)
3009#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
3010#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
3011#define CAN_F5R1_FB6_Pos (6U)
3012#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
3013#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
3014#define CAN_F5R1_FB7_Pos (7U)
3015#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
3016#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
3017#define CAN_F5R1_FB8_Pos (8U)
3018#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
3019#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
3020#define CAN_F5R1_FB9_Pos (9U)
3021#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
3022#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
3023#define CAN_F5R1_FB10_Pos (10U)
3024#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
3025#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
3026#define CAN_F5R1_FB11_Pos (11U)
3027#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
3028#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
3029#define CAN_F5R1_FB12_Pos (12U)
3030#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
3031#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
3032#define CAN_F5R1_FB13_Pos (13U)
3033#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
3034#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
3035#define CAN_F5R1_FB14_Pos (14U)
3036#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
3037#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
3038#define CAN_F5R1_FB15_Pos (15U)
3039#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
3040#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
3041#define CAN_F5R1_FB16_Pos (16U)
3042#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
3043#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
3044#define CAN_F5R1_FB17_Pos (17U)
3045#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
3046#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
3047#define CAN_F5R1_FB18_Pos (18U)
3048#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
3049#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
3050#define CAN_F5R1_FB19_Pos (19U)
3051#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
3052#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
3053#define CAN_F5R1_FB20_Pos (20U)
3054#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
3055#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
3056#define CAN_F5R1_FB21_Pos (21U)
3057#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
3058#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
3059#define CAN_F5R1_FB22_Pos (22U)
3060#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
3061#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
3062#define CAN_F5R1_FB23_Pos (23U)
3063#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
3064#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
3065#define CAN_F5R1_FB24_Pos (24U)
3066#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
3067#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
3068#define CAN_F5R1_FB25_Pos (25U)
3069#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
3070#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
3071#define CAN_F5R1_FB26_Pos (26U)
3072#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
3073#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
3074#define CAN_F5R1_FB27_Pos (27U)
3075#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
3076#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
3077#define CAN_F5R1_FB28_Pos (28U)
3078#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
3079#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
3080#define CAN_F5R1_FB29_Pos (29U)
3081#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
3082#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
3083#define CAN_F5R1_FB30_Pos (30U)
3084#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
3085#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
3086#define CAN_F5R1_FB31_Pos (31U)
3087#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
3088#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
3090/******************* Bit definition for CAN_F6R1 register *******************/
3091#define CAN_F6R1_FB0_Pos (0U)
3092#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
3093#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
3094#define CAN_F6R1_FB1_Pos (1U)
3095#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
3096#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
3097#define CAN_F6R1_FB2_Pos (2U)
3098#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
3099#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
3100#define CAN_F6R1_FB3_Pos (3U)
3101#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
3102#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
3103#define CAN_F6R1_FB4_Pos (4U)
3104#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
3105#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
3106#define CAN_F6R1_FB5_Pos (5U)
3107#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
3108#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
3109#define CAN_F6R1_FB6_Pos (6U)
3110#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
3111#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
3112#define CAN_F6R1_FB7_Pos (7U)
3113#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
3114#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
3115#define CAN_F6R1_FB8_Pos (8U)
3116#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
3117#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
3118#define CAN_F6R1_FB9_Pos (9U)
3119#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
3120#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
3121#define CAN_F6R1_FB10_Pos (10U)
3122#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
3123#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
3124#define CAN_F6R1_FB11_Pos (11U)
3125#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
3126#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
3127#define CAN_F6R1_FB12_Pos (12U)
3128#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
3129#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
3130#define CAN_F6R1_FB13_Pos (13U)
3131#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
3132#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
3133#define CAN_F6R1_FB14_Pos (14U)
3134#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
3135#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
3136#define CAN_F6R1_FB15_Pos (15U)
3137#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
3138#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
3139#define CAN_F6R1_FB16_Pos (16U)
3140#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
3141#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
3142#define CAN_F6R1_FB17_Pos (17U)
3143#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
3144#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
3145#define CAN_F6R1_FB18_Pos (18U)
3146#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
3147#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
3148#define CAN_F6R1_FB19_Pos (19U)
3149#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
3150#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
3151#define CAN_F6R1_FB20_Pos (20U)
3152#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
3153#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
3154#define CAN_F6R1_FB21_Pos (21U)
3155#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
3156#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
3157#define CAN_F6R1_FB22_Pos (22U)
3158#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
3159#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
3160#define CAN_F6R1_FB23_Pos (23U)
3161#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
3162#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
3163#define CAN_F6R1_FB24_Pos (24U)
3164#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
3165#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
3166#define CAN_F6R1_FB25_Pos (25U)
3167#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
3168#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
3169#define CAN_F6R1_FB26_Pos (26U)
3170#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
3171#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
3172#define CAN_F6R1_FB27_Pos (27U)
3173#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
3174#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
3175#define CAN_F6R1_FB28_Pos (28U)
3176#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
3177#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
3178#define CAN_F6R1_FB29_Pos (29U)
3179#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
3180#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
3181#define CAN_F6R1_FB30_Pos (30U)
3182#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
3183#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
3184#define CAN_F6R1_FB31_Pos (31U)
3185#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
3186#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
3188/******************* Bit definition for CAN_F7R1 register *******************/
3189#define CAN_F7R1_FB0_Pos (0U)
3190#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
3191#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
3192#define CAN_F7R1_FB1_Pos (1U)
3193#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
3194#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
3195#define CAN_F7R1_FB2_Pos (2U)
3196#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
3197#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
3198#define CAN_F7R1_FB3_Pos (3U)
3199#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
3200#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
3201#define CAN_F7R1_FB4_Pos (4U)
3202#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
3203#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
3204#define CAN_F7R1_FB5_Pos (5U)
3205#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
3206#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
3207#define CAN_F7R1_FB6_Pos (6U)
3208#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
3209#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
3210#define CAN_F7R1_FB7_Pos (7U)
3211#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
3212#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
3213#define CAN_F7R1_FB8_Pos (8U)
3214#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
3215#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
3216#define CAN_F7R1_FB9_Pos (9U)
3217#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
3218#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
3219#define CAN_F7R1_FB10_Pos (10U)
3220#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
3221#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
3222#define CAN_F7R1_FB11_Pos (11U)
3223#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
3224#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
3225#define CAN_F7R1_FB12_Pos (12U)
3226#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
3227#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
3228#define CAN_F7R1_FB13_Pos (13U)
3229#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
3230#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
3231#define CAN_F7R1_FB14_Pos (14U)
3232#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
3233#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
3234#define CAN_F7R1_FB15_Pos (15U)
3235#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
3236#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
3237#define CAN_F7R1_FB16_Pos (16U)
3238#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
3239#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
3240#define CAN_F7R1_FB17_Pos (17U)
3241#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
3242#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
3243#define CAN_F7R1_FB18_Pos (18U)
3244#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
3245#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
3246#define CAN_F7R1_FB19_Pos (19U)
3247#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
3248#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
3249#define CAN_F7R1_FB20_Pos (20U)
3250#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
3251#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
3252#define CAN_F7R1_FB21_Pos (21U)
3253#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
3254#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
3255#define CAN_F7R1_FB22_Pos (22U)
3256#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
3257#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
3258#define CAN_F7R1_FB23_Pos (23U)
3259#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
3260#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
3261#define CAN_F7R1_FB24_Pos (24U)
3262#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
3263#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
3264#define CAN_F7R1_FB25_Pos (25U)
3265#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
3266#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
3267#define CAN_F7R1_FB26_Pos (26U)
3268#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
3269#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
3270#define CAN_F7R1_FB27_Pos (27U)
3271#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
3272#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
3273#define CAN_F7R1_FB28_Pos (28U)
3274#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
3275#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
3276#define CAN_F7R1_FB29_Pos (29U)
3277#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
3278#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
3279#define CAN_F7R1_FB30_Pos (30U)
3280#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
3281#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
3282#define CAN_F7R1_FB31_Pos (31U)
3283#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
3284#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
3286/******************* Bit definition for CAN_F8R1 register *******************/
3287#define CAN_F8R1_FB0_Pos (0U)
3288#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
3289#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
3290#define CAN_F8R1_FB1_Pos (1U)
3291#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
3292#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
3293#define CAN_F8R1_FB2_Pos (2U)
3294#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
3295#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
3296#define CAN_F8R1_FB3_Pos (3U)
3297#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
3298#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
3299#define CAN_F8R1_FB4_Pos (4U)
3300#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
3301#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
3302#define CAN_F8R1_FB5_Pos (5U)
3303#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
3304#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
3305#define CAN_F8R1_FB6_Pos (6U)
3306#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
3307#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
3308#define CAN_F8R1_FB7_Pos (7U)
3309#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
3310#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
3311#define CAN_F8R1_FB8_Pos (8U)
3312#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
3313#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
3314#define CAN_F8R1_FB9_Pos (9U)
3315#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
3316#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
3317#define CAN_F8R1_FB10_Pos (10U)
3318#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
3319#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
3320#define CAN_F8R1_FB11_Pos (11U)
3321#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
3322#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
3323#define CAN_F8R1_FB12_Pos (12U)
3324#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
3325#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
3326#define CAN_F8R1_FB13_Pos (13U)
3327#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
3328#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
3329#define CAN_F8R1_FB14_Pos (14U)
3330#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
3331#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
3332#define CAN_F8R1_FB15_Pos (15U)
3333#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
3334#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
3335#define CAN_F8R1_FB16_Pos (16U)
3336#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
3337#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
3338#define CAN_F8R1_FB17_Pos (17U)
3339#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
3340#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
3341#define CAN_F8R1_FB18_Pos (18U)
3342#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
3343#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
3344#define CAN_F8R1_FB19_Pos (19U)
3345#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
3346#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
3347#define CAN_F8R1_FB20_Pos (20U)
3348#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
3349#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
3350#define CAN_F8R1_FB21_Pos (21U)
3351#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
3352#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
3353#define CAN_F8R1_FB22_Pos (22U)
3354#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
3355#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
3356#define CAN_F8R1_FB23_Pos (23U)
3357#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
3358#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
3359#define CAN_F8R1_FB24_Pos (24U)
3360#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
3361#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
3362#define CAN_F8R1_FB25_Pos (25U)
3363#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
3364#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
3365#define CAN_F8R1_FB26_Pos (26U)
3366#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
3367#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
3368#define CAN_F8R1_FB27_Pos (27U)
3369#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
3370#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
3371#define CAN_F8R1_FB28_Pos (28U)
3372#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
3373#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
3374#define CAN_F8R1_FB29_Pos (29U)
3375#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
3376#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
3377#define CAN_F8R1_FB30_Pos (30U)
3378#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
3379#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
3380#define CAN_F8R1_FB31_Pos (31U)
3381#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
3382#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
3384/******************* Bit definition for CAN_F9R1 register *******************/
3385#define CAN_F9R1_FB0_Pos (0U)
3386#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
3387#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
3388#define CAN_F9R1_FB1_Pos (1U)
3389#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
3390#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
3391#define CAN_F9R1_FB2_Pos (2U)
3392#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
3393#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
3394#define CAN_F9R1_FB3_Pos (3U)
3395#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
3396#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
3397#define CAN_F9R1_FB4_Pos (4U)
3398#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
3399#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
3400#define CAN_F9R1_FB5_Pos (5U)
3401#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
3402#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
3403#define CAN_F9R1_FB6_Pos (6U)
3404#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
3405#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
3406#define CAN_F9R1_FB7_Pos (7U)
3407#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
3408#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
3409#define CAN_F9R1_FB8_Pos (8U)
3410#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
3411#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
3412#define CAN_F9R1_FB9_Pos (9U)
3413#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
3414#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
3415#define CAN_F9R1_FB10_Pos (10U)
3416#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
3417#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
3418#define CAN_F9R1_FB11_Pos (11U)
3419#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
3420#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
3421#define CAN_F9R1_FB12_Pos (12U)
3422#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
3423#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
3424#define CAN_F9R1_FB13_Pos (13U)
3425#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
3426#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
3427#define CAN_F9R1_FB14_Pos (14U)
3428#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
3429#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
3430#define CAN_F9R1_FB15_Pos (15U)
3431#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
3432#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
3433#define CAN_F9R1_FB16_Pos (16U)
3434#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
3435#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
3436#define CAN_F9R1_FB17_Pos (17U)
3437#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
3438#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
3439#define CAN_F9R1_FB18_Pos (18U)
3440#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
3441#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
3442#define CAN_F9R1_FB19_Pos (19U)
3443#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
3444#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
3445#define CAN_F9R1_FB20_Pos (20U)
3446#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
3447#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
3448#define CAN_F9R1_FB21_Pos (21U)
3449#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
3450#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
3451#define CAN_F9R1_FB22_Pos (22U)
3452#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
3453#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
3454#define CAN_F9R1_FB23_Pos (23U)
3455#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
3456#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
3457#define CAN_F9R1_FB24_Pos (24U)
3458#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
3459#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
3460#define CAN_F9R1_FB25_Pos (25U)
3461#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
3462#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
3463#define CAN_F9R1_FB26_Pos (26U)
3464#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
3465#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
3466#define CAN_F9R1_FB27_Pos (27U)
3467#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
3468#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
3469#define CAN_F9R1_FB28_Pos (28U)
3470#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
3471#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
3472#define CAN_F9R1_FB29_Pos (29U)
3473#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
3474#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
3475#define CAN_F9R1_FB30_Pos (30U)
3476#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
3477#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
3478#define CAN_F9R1_FB31_Pos (31U)
3479#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
3480#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
3482/******************* Bit definition for CAN_F10R1 register ******************/
3483#define CAN_F10R1_FB0_Pos (0U)
3484#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
3485#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
3486#define CAN_F10R1_FB1_Pos (1U)
3487#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
3488#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
3489#define CAN_F10R1_FB2_Pos (2U)
3490#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
3491#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
3492#define CAN_F10R1_FB3_Pos (3U)
3493#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
3494#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
3495#define CAN_F10R1_FB4_Pos (4U)
3496#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
3497#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
3498#define CAN_F10R1_FB5_Pos (5U)
3499#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
3500#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
3501#define CAN_F10R1_FB6_Pos (6U)
3502#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
3503#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
3504#define CAN_F10R1_FB7_Pos (7U)
3505#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
3506#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
3507#define CAN_F10R1_FB8_Pos (8U)
3508#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
3509#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
3510#define CAN_F10R1_FB9_Pos (9U)
3511#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
3512#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
3513#define CAN_F10R1_FB10_Pos (10U)
3514#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
3515#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
3516#define CAN_F10R1_FB11_Pos (11U)
3517#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
3518#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
3519#define CAN_F10R1_FB12_Pos (12U)
3520#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
3521#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
3522#define CAN_F10R1_FB13_Pos (13U)
3523#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
3524#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
3525#define CAN_F10R1_FB14_Pos (14U)
3526#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
3527#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
3528#define CAN_F10R1_FB15_Pos (15U)
3529#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
3530#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
3531#define CAN_F10R1_FB16_Pos (16U)
3532#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
3533#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
3534#define CAN_F10R1_FB17_Pos (17U)
3535#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
3536#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
3537#define CAN_F10R1_FB18_Pos (18U)
3538#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
3539#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
3540#define CAN_F10R1_FB19_Pos (19U)
3541#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
3542#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
3543#define CAN_F10R1_FB20_Pos (20U)
3544#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
3545#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
3546#define CAN_F10R1_FB21_Pos (21U)
3547#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
3548#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
3549#define CAN_F10R1_FB22_Pos (22U)
3550#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
3551#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
3552#define CAN_F10R1_FB23_Pos (23U)
3553#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
3554#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
3555#define CAN_F10R1_FB24_Pos (24U)
3556#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
3557#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
3558#define CAN_F10R1_FB25_Pos (25U)
3559#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
3560#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
3561#define CAN_F10R1_FB26_Pos (26U)
3562#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
3563#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
3564#define CAN_F10R1_FB27_Pos (27U)
3565#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
3566#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
3567#define CAN_F10R1_FB28_Pos (28U)
3568#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
3569#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
3570#define CAN_F10R1_FB29_Pos (29U)
3571#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
3572#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
3573#define CAN_F10R1_FB30_Pos (30U)
3574#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
3575#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
3576#define CAN_F10R1_FB31_Pos (31U)
3577#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
3578#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
3580/******************* Bit definition for CAN_F11R1 register ******************/
3581#define CAN_F11R1_FB0_Pos (0U)
3582#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
3583#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
3584#define CAN_F11R1_FB1_Pos (1U)
3585#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
3586#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
3587#define CAN_F11R1_FB2_Pos (2U)
3588#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
3589#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
3590#define CAN_F11R1_FB3_Pos (3U)
3591#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
3592#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
3593#define CAN_F11R1_FB4_Pos (4U)
3594#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
3595#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
3596#define CAN_F11R1_FB5_Pos (5U)
3597#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
3598#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
3599#define CAN_F11R1_FB6_Pos (6U)
3600#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
3601#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
3602#define CAN_F11R1_FB7_Pos (7U)
3603#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
3604#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
3605#define CAN_F11R1_FB8_Pos (8U)
3606#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
3607#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
3608#define CAN_F11R1_FB9_Pos (9U)
3609#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
3610#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
3611#define CAN_F11R1_FB10_Pos (10U)
3612#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
3613#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
3614#define CAN_F11R1_FB11_Pos (11U)
3615#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
3616#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
3617#define CAN_F11R1_FB12_Pos (12U)
3618#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
3619#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
3620#define CAN_F11R1_FB13_Pos (13U)
3621#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
3622#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
3623#define CAN_F11R1_FB14_Pos (14U)
3624#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
3625#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
3626#define CAN_F11R1_FB15_Pos (15U)
3627#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
3628#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
3629#define CAN_F11R1_FB16_Pos (16U)
3630#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
3631#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
3632#define CAN_F11R1_FB17_Pos (17U)
3633#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
3634#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
3635#define CAN_F11R1_FB18_Pos (18U)
3636#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
3637#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
3638#define CAN_F11R1_FB19_Pos (19U)
3639#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
3640#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
3641#define CAN_F11R1_FB20_Pos (20U)
3642#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
3643#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
3644#define CAN_F11R1_FB21_Pos (21U)
3645#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
3646#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
3647#define CAN_F11R1_FB22_Pos (22U)
3648#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
3649#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
3650#define CAN_F11R1_FB23_Pos (23U)
3651#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
3652#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
3653#define CAN_F11R1_FB24_Pos (24U)
3654#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
3655#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
3656#define CAN_F11R1_FB25_Pos (25U)
3657#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
3658#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
3659#define CAN_F11R1_FB26_Pos (26U)
3660#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
3661#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
3662#define CAN_F11R1_FB27_Pos (27U)
3663#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
3664#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
3665#define CAN_F11R1_FB28_Pos (28U)
3666#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
3667#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
3668#define CAN_F11R1_FB29_Pos (29U)
3669#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
3670#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
3671#define CAN_F11R1_FB30_Pos (30U)
3672#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
3673#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
3674#define CAN_F11R1_FB31_Pos (31U)
3675#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
3676#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
3678/******************* Bit definition for CAN_F12R1 register ******************/
3679#define CAN_F12R1_FB0_Pos (0U)
3680#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
3681#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
3682#define CAN_F12R1_FB1_Pos (1U)
3683#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
3684#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
3685#define CAN_F12R1_FB2_Pos (2U)
3686#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
3687#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
3688#define CAN_F12R1_FB3_Pos (3U)
3689#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
3690#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
3691#define CAN_F12R1_FB4_Pos (4U)
3692#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
3693#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
3694#define CAN_F12R1_FB5_Pos (5U)
3695#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
3696#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
3697#define CAN_F12R1_FB6_Pos (6U)
3698#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
3699#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
3700#define CAN_F12R1_FB7_Pos (7U)
3701#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
3702#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
3703#define CAN_F12R1_FB8_Pos (8U)
3704#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
3705#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
3706#define CAN_F12R1_FB9_Pos (9U)
3707#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
3708#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
3709#define CAN_F12R1_FB10_Pos (10U)
3710#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
3711#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
3712#define CAN_F12R1_FB11_Pos (11U)
3713#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
3714#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
3715#define CAN_F12R1_FB12_Pos (12U)
3716#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
3717#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
3718#define CAN_F12R1_FB13_Pos (13U)
3719#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
3720#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
3721#define CAN_F12R1_FB14_Pos (14U)
3722#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
3723#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
3724#define CAN_F12R1_FB15_Pos (15U)
3725#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
3726#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
3727#define CAN_F12R1_FB16_Pos (16U)
3728#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
3729#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
3730#define CAN_F12R1_FB17_Pos (17U)
3731#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
3732#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
3733#define CAN_F12R1_FB18_Pos (18U)
3734#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
3735#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
3736#define CAN_F12R1_FB19_Pos (19U)
3737#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
3738#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
3739#define CAN_F12R1_FB20_Pos (20U)
3740#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
3741#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
3742#define CAN_F12R1_FB21_Pos (21U)
3743#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
3744#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
3745#define CAN_F12R1_FB22_Pos (22U)
3746#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
3747#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
3748#define CAN_F12R1_FB23_Pos (23U)
3749#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
3750#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
3751#define CAN_F12R1_FB24_Pos (24U)
3752#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
3753#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
3754#define CAN_F12R1_FB25_Pos (25U)
3755#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
3756#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
3757#define CAN_F12R1_FB26_Pos (26U)
3758#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
3759#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
3760#define CAN_F12R1_FB27_Pos (27U)
3761#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
3762#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
3763#define CAN_F12R1_FB28_Pos (28U)
3764#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
3765#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
3766#define CAN_F12R1_FB29_Pos (29U)
3767#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
3768#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
3769#define CAN_F12R1_FB30_Pos (30U)
3770#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
3771#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
3772#define CAN_F12R1_FB31_Pos (31U)
3773#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
3774#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
3776/******************* Bit definition for CAN_F13R1 register ******************/
3777#define CAN_F13R1_FB0_Pos (0U)
3778#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
3779#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
3780#define CAN_F13R1_FB1_Pos (1U)
3781#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
3782#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
3783#define CAN_F13R1_FB2_Pos (2U)
3784#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
3785#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
3786#define CAN_F13R1_FB3_Pos (3U)
3787#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
3788#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
3789#define CAN_F13R1_FB4_Pos (4U)
3790#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
3791#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
3792#define CAN_F13R1_FB5_Pos (5U)
3793#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
3794#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
3795#define CAN_F13R1_FB6_Pos (6U)
3796#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
3797#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
3798#define CAN_F13R1_FB7_Pos (7U)
3799#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
3800#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
3801#define CAN_F13R1_FB8_Pos (8U)
3802#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
3803#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
3804#define CAN_F13R1_FB9_Pos (9U)
3805#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
3806#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
3807#define CAN_F13R1_FB10_Pos (10U)
3808#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
3809#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
3810#define CAN_F13R1_FB11_Pos (11U)
3811#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
3812#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
3813#define CAN_F13R1_FB12_Pos (12U)
3814#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
3815#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
3816#define CAN_F13R1_FB13_Pos (13U)
3817#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
3818#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
3819#define CAN_F13R1_FB14_Pos (14U)
3820#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
3821#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
3822#define CAN_F13R1_FB15_Pos (15U)
3823#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
3824#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
3825#define CAN_F13R1_FB16_Pos (16U)
3826#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
3827#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
3828#define CAN_F13R1_FB17_Pos (17U)
3829#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
3830#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
3831#define CAN_F13R1_FB18_Pos (18U)
3832#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
3833#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
3834#define CAN_F13R1_FB19_Pos (19U)
3835#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
3836#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
3837#define CAN_F13R1_FB20_Pos (20U)
3838#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
3839#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
3840#define CAN_F13R1_FB21_Pos (21U)
3841#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
3842#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
3843#define CAN_F13R1_FB22_Pos (22U)
3844#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
3845#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
3846#define CAN_F13R1_FB23_Pos (23U)
3847#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
3848#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
3849#define CAN_F13R1_FB24_Pos (24U)
3850#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
3851#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
3852#define CAN_F13R1_FB25_Pos (25U)
3853#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
3854#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
3855#define CAN_F13R1_FB26_Pos (26U)
3856#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
3857#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
3858#define CAN_F13R1_FB27_Pos (27U)
3859#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
3860#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
3861#define CAN_F13R1_FB28_Pos (28U)
3862#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
3863#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
3864#define CAN_F13R1_FB29_Pos (29U)
3865#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
3866#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
3867#define CAN_F13R1_FB30_Pos (30U)
3868#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
3869#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
3870#define CAN_F13R1_FB31_Pos (31U)
3871#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
3872#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
3874/******************* Bit definition for CAN_F0R2 register *******************/
3875#define CAN_F0R2_FB0_Pos (0U)
3876#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
3877#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
3878#define CAN_F0R2_FB1_Pos (1U)
3879#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
3880#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
3881#define CAN_F0R2_FB2_Pos (2U)
3882#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
3883#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
3884#define CAN_F0R2_FB3_Pos (3U)
3885#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
3886#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
3887#define CAN_F0R2_FB4_Pos (4U)
3888#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
3889#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
3890#define CAN_F0R2_FB5_Pos (5U)
3891#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
3892#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
3893#define CAN_F0R2_FB6_Pos (6U)
3894#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
3895#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
3896#define CAN_F0R2_FB7_Pos (7U)
3897#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
3898#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
3899#define CAN_F0R2_FB8_Pos (8U)
3900#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
3901#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
3902#define CAN_F0R2_FB9_Pos (9U)
3903#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
3904#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
3905#define CAN_F0R2_FB10_Pos (10U)
3906#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
3907#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
3908#define CAN_F0R2_FB11_Pos (11U)
3909#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
3910#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
3911#define CAN_F0R2_FB12_Pos (12U)
3912#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
3913#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
3914#define CAN_F0R2_FB13_Pos (13U)
3915#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
3916#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
3917#define CAN_F0R2_FB14_Pos (14U)
3918#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
3919#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
3920#define CAN_F0R2_FB15_Pos (15U)
3921#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
3922#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
3923#define CAN_F0R2_FB16_Pos (16U)
3924#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
3925#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
3926#define CAN_F0R2_FB17_Pos (17U)
3927#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
3928#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
3929#define CAN_F0R2_FB18_Pos (18U)
3930#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
3931#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
3932#define CAN_F0R2_FB19_Pos (19U)
3933#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
3934#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
3935#define CAN_F0R2_FB20_Pos (20U)
3936#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
3937#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
3938#define CAN_F0R2_FB21_Pos (21U)
3939#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
3940#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
3941#define CAN_F0R2_FB22_Pos (22U)
3942#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
3943#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
3944#define CAN_F0R2_FB23_Pos (23U)
3945#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
3946#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
3947#define CAN_F0R2_FB24_Pos (24U)
3948#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
3949#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
3950#define CAN_F0R2_FB25_Pos (25U)
3951#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
3952#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
3953#define CAN_F0R2_FB26_Pos (26U)
3954#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
3955#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
3956#define CAN_F0R2_FB27_Pos (27U)
3957#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
3958#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
3959#define CAN_F0R2_FB28_Pos (28U)
3960#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
3961#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
3962#define CAN_F0R2_FB29_Pos (29U)
3963#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
3964#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
3965#define CAN_F0R2_FB30_Pos (30U)
3966#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
3967#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
3968#define CAN_F0R2_FB31_Pos (31U)
3969#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
3970#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
3972/******************* Bit definition for CAN_F1R2 register *******************/
3973#define CAN_F1R2_FB0_Pos (0U)
3974#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
3975#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
3976#define CAN_F1R2_FB1_Pos (1U)
3977#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
3978#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
3979#define CAN_F1R2_FB2_Pos (2U)
3980#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
3981#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
3982#define CAN_F1R2_FB3_Pos (3U)
3983#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
3984#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
3985#define CAN_F1R2_FB4_Pos (4U)
3986#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
3987#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
3988#define CAN_F1R2_FB5_Pos (5U)
3989#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
3990#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
3991#define CAN_F1R2_FB6_Pos (6U)
3992#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
3993#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
3994#define CAN_F1R2_FB7_Pos (7U)
3995#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
3996#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
3997#define CAN_F1R2_FB8_Pos (8U)
3998#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
3999#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
4000#define CAN_F1R2_FB9_Pos (9U)
4001#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
4002#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
4003#define CAN_F1R2_FB10_Pos (10U)
4004#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
4005#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
4006#define CAN_F1R2_FB11_Pos (11U)
4007#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
4008#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
4009#define CAN_F1R2_FB12_Pos (12U)
4010#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
4011#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
4012#define CAN_F1R2_FB13_Pos (13U)
4013#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
4014#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
4015#define CAN_F1R2_FB14_Pos (14U)
4016#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
4017#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
4018#define CAN_F1R2_FB15_Pos (15U)
4019#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
4020#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
4021#define CAN_F1R2_FB16_Pos (16U)
4022#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
4023#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
4024#define CAN_F1R2_FB17_Pos (17U)
4025#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
4026#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
4027#define CAN_F1R2_FB18_Pos (18U)
4028#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
4029#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
4030#define CAN_F1R2_FB19_Pos (19U)
4031#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
4032#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
4033#define CAN_F1R2_FB20_Pos (20U)
4034#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
4035#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
4036#define CAN_F1R2_FB21_Pos (21U)
4037#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
4038#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
4039#define CAN_F1R2_FB22_Pos (22U)
4040#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
4041#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
4042#define CAN_F1R2_FB23_Pos (23U)
4043#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
4044#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
4045#define CAN_F1R2_FB24_Pos (24U)
4046#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
4047#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
4048#define CAN_F1R2_FB25_Pos (25U)
4049#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
4050#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
4051#define CAN_F1R2_FB26_Pos (26U)
4052#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
4053#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
4054#define CAN_F1R2_FB27_Pos (27U)
4055#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
4056#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
4057#define CAN_F1R2_FB28_Pos (28U)
4058#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
4059#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
4060#define CAN_F1R2_FB29_Pos (29U)
4061#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
4062#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
4063#define CAN_F1R2_FB30_Pos (30U)
4064#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
4065#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
4066#define CAN_F1R2_FB31_Pos (31U)
4067#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
4068#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
4070/******************* Bit definition for CAN_F2R2 register *******************/
4071#define CAN_F2R2_FB0_Pos (0U)
4072#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
4073#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
4074#define CAN_F2R2_FB1_Pos (1U)
4075#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
4076#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
4077#define CAN_F2R2_FB2_Pos (2U)
4078#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
4079#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
4080#define CAN_F2R2_FB3_Pos (3U)
4081#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
4082#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
4083#define CAN_F2R2_FB4_Pos (4U)
4084#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
4085#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
4086#define CAN_F2R2_FB5_Pos (5U)
4087#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
4088#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
4089#define CAN_F2R2_FB6_Pos (6U)
4090#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
4091#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
4092#define CAN_F2R2_FB7_Pos (7U)
4093#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
4094#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
4095#define CAN_F2R2_FB8_Pos (8U)
4096#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
4097#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
4098#define CAN_F2R2_FB9_Pos (9U)
4099#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
4100#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
4101#define CAN_F2R2_FB10_Pos (10U)
4102#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
4103#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
4104#define CAN_F2R2_FB11_Pos (11U)
4105#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
4106#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
4107#define CAN_F2R2_FB12_Pos (12U)
4108#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
4109#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
4110#define CAN_F2R2_FB13_Pos (13U)
4111#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
4112#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
4113#define CAN_F2R2_FB14_Pos (14U)
4114#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
4115#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
4116#define CAN_F2R2_FB15_Pos (15U)
4117#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
4118#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
4119#define CAN_F2R2_FB16_Pos (16U)
4120#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
4121#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
4122#define CAN_F2R2_FB17_Pos (17U)
4123#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
4124#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
4125#define CAN_F2R2_FB18_Pos (18U)
4126#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
4127#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
4128#define CAN_F2R2_FB19_Pos (19U)
4129#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
4130#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
4131#define CAN_F2R2_FB20_Pos (20U)
4132#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
4133#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
4134#define CAN_F2R2_FB21_Pos (21U)
4135#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
4136#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
4137#define CAN_F2R2_FB22_Pos (22U)
4138#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
4139#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
4140#define CAN_F2R2_FB23_Pos (23U)
4141#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
4142#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
4143#define CAN_F2R2_FB24_Pos (24U)
4144#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
4145#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
4146#define CAN_F2R2_FB25_Pos (25U)
4147#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
4148#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
4149#define CAN_F2R2_FB26_Pos (26U)
4150#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
4151#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
4152#define CAN_F2R2_FB27_Pos (27U)
4153#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
4154#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
4155#define CAN_F2R2_FB28_Pos (28U)
4156#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
4157#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
4158#define CAN_F2R2_FB29_Pos (29U)
4159#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
4160#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
4161#define CAN_F2R2_FB30_Pos (30U)
4162#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
4163#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
4164#define CAN_F2R2_FB31_Pos (31U)
4165#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
4166#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
4168/******************* Bit definition for CAN_F3R2 register *******************/
4169#define CAN_F3R2_FB0_Pos (0U)
4170#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
4171#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
4172#define CAN_F3R2_FB1_Pos (1U)
4173#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
4174#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
4175#define CAN_F3R2_FB2_Pos (2U)
4176#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
4177#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
4178#define CAN_F3R2_FB3_Pos (3U)
4179#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
4180#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
4181#define CAN_F3R2_FB4_Pos (4U)
4182#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
4183#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
4184#define CAN_F3R2_FB5_Pos (5U)
4185#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
4186#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
4187#define CAN_F3R2_FB6_Pos (6U)
4188#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
4189#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
4190#define CAN_F3R2_FB7_Pos (7U)
4191#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
4192#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
4193#define CAN_F3R2_FB8_Pos (8U)
4194#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
4195#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
4196#define CAN_F3R2_FB9_Pos (9U)
4197#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
4198#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
4199#define CAN_F3R2_FB10_Pos (10U)
4200#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
4201#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
4202#define CAN_F3R2_FB11_Pos (11U)
4203#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
4204#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
4205#define CAN_F3R2_FB12_Pos (12U)
4206#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
4207#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
4208#define CAN_F3R2_FB13_Pos (13U)
4209#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
4210#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
4211#define CAN_F3R2_FB14_Pos (14U)
4212#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
4213#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
4214#define CAN_F3R2_FB15_Pos (15U)
4215#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
4216#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
4217#define CAN_F3R2_FB16_Pos (16U)
4218#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
4219#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
4220#define CAN_F3R2_FB17_Pos (17U)
4221#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
4222#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
4223#define CAN_F3R2_FB18_Pos (18U)
4224#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
4225#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
4226#define CAN_F3R2_FB19_Pos (19U)
4227#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
4228#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
4229#define CAN_F3R2_FB20_Pos (20U)
4230#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
4231#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
4232#define CAN_F3R2_FB21_Pos (21U)
4233#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
4234#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
4235#define CAN_F3R2_FB22_Pos (22U)
4236#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
4237#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
4238#define CAN_F3R2_FB23_Pos (23U)
4239#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
4240#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
4241#define CAN_F3R2_FB24_Pos (24U)
4242#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
4243#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
4244#define CAN_F3R2_FB25_Pos (25U)
4245#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
4246#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
4247#define CAN_F3R2_FB26_Pos (26U)
4248#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
4249#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
4250#define CAN_F3R2_FB27_Pos (27U)
4251#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
4252#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
4253#define CAN_F3R2_FB28_Pos (28U)
4254#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
4255#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
4256#define CAN_F3R2_FB29_Pos (29U)
4257#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
4258#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
4259#define CAN_F3R2_FB30_Pos (30U)
4260#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
4261#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
4262#define CAN_F3R2_FB31_Pos (31U)
4263#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
4264#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
4266/******************* Bit definition for CAN_F4R2 register *******************/
4267#define CAN_F4R2_FB0_Pos (0U)
4268#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
4269#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
4270#define CAN_F4R2_FB1_Pos (1U)
4271#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
4272#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
4273#define CAN_F4R2_FB2_Pos (2U)
4274#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
4275#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
4276#define CAN_F4R2_FB3_Pos (3U)
4277#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
4278#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
4279#define CAN_F4R2_FB4_Pos (4U)
4280#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
4281#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
4282#define CAN_F4R2_FB5_Pos (5U)
4283#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
4284#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
4285#define CAN_F4R2_FB6_Pos (6U)
4286#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
4287#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
4288#define CAN_F4R2_FB7_Pos (7U)
4289#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
4290#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
4291#define CAN_F4R2_FB8_Pos (8U)
4292#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
4293#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
4294#define CAN_F4R2_FB9_Pos (9U)
4295#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
4296#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
4297#define CAN_F4R2_FB10_Pos (10U)
4298#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
4299#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
4300#define CAN_F4R2_FB11_Pos (11U)
4301#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
4302#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
4303#define CAN_F4R2_FB12_Pos (12U)
4304#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
4305#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
4306#define CAN_F4R2_FB13_Pos (13U)
4307#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
4308#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
4309#define CAN_F4R2_FB14_Pos (14U)
4310#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
4311#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
4312#define CAN_F4R2_FB15_Pos (15U)
4313#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
4314#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
4315#define CAN_F4R2_FB16_Pos (16U)
4316#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
4317#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
4318#define CAN_F4R2_FB17_Pos (17U)
4319#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
4320#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
4321#define CAN_F4R2_FB18_Pos (18U)
4322#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
4323#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
4324#define CAN_F4R2_FB19_Pos (19U)
4325#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
4326#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
4327#define CAN_F4R2_FB20_Pos (20U)
4328#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
4329#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
4330#define CAN_F4R2_FB21_Pos (21U)
4331#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
4332#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
4333#define CAN_F4R2_FB22_Pos (22U)
4334#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
4335#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
4336#define CAN_F4R2_FB23_Pos (23U)
4337#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
4338#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
4339#define CAN_F4R2_FB24_Pos (24U)
4340#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
4341#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
4342#define CAN_F4R2_FB25_Pos (25U)
4343#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
4344#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
4345#define CAN_F4R2_FB26_Pos (26U)
4346#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
4347#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
4348#define CAN_F4R2_FB27_Pos (27U)
4349#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
4350#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
4351#define CAN_F4R2_FB28_Pos (28U)
4352#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
4353#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
4354#define CAN_F4R2_FB29_Pos (29U)
4355#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
4356#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
4357#define CAN_F4R2_FB30_Pos (30U)
4358#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
4359#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
4360#define CAN_F4R2_FB31_Pos (31U)
4361#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
4362#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
4364/******************* Bit definition for CAN_F5R2 register *******************/
4365#define CAN_F5R2_FB0_Pos (0U)
4366#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
4367#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
4368#define CAN_F5R2_FB1_Pos (1U)
4369#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
4370#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
4371#define CAN_F5R2_FB2_Pos (2U)
4372#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
4373#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
4374#define CAN_F5R2_FB3_Pos (3U)
4375#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
4376#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
4377#define CAN_F5R2_FB4_Pos (4U)
4378#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
4379#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
4380#define CAN_F5R2_FB5_Pos (5U)
4381#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
4382#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
4383#define CAN_F5R2_FB6_Pos (6U)
4384#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
4385#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
4386#define CAN_F5R2_FB7_Pos (7U)
4387#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
4388#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
4389#define CAN_F5R2_FB8_Pos (8U)
4390#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
4391#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
4392#define CAN_F5R2_FB9_Pos (9U)
4393#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
4394#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
4395#define CAN_F5R2_FB10_Pos (10U)
4396#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
4397#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
4398#define CAN_F5R2_FB11_Pos (11U)
4399#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
4400#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
4401#define CAN_F5R2_FB12_Pos (12U)
4402#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
4403#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
4404#define CAN_F5R2_FB13_Pos (13U)
4405#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
4406#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
4407#define CAN_F5R2_FB14_Pos (14U)
4408#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
4409#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
4410#define CAN_F5R2_FB15_Pos (15U)
4411#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
4412#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
4413#define CAN_F5R2_FB16_Pos (16U)
4414#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
4415#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
4416#define CAN_F5R2_FB17_Pos (17U)
4417#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
4418#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
4419#define CAN_F5R2_FB18_Pos (18U)
4420#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
4421#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
4422#define CAN_F5R2_FB19_Pos (19U)
4423#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
4424#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
4425#define CAN_F5R2_FB20_Pos (20U)
4426#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
4427#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
4428#define CAN_F5R2_FB21_Pos (21U)
4429#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
4430#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
4431#define CAN_F5R2_FB22_Pos (22U)
4432#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
4433#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
4434#define CAN_F5R2_FB23_Pos (23U)
4435#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
4436#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
4437#define CAN_F5R2_FB24_Pos (24U)
4438#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
4439#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
4440#define CAN_F5R2_FB25_Pos (25U)
4441#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
4442#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
4443#define CAN_F5R2_FB26_Pos (26U)
4444#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
4445#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
4446#define CAN_F5R2_FB27_Pos (27U)
4447#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
4448#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
4449#define CAN_F5R2_FB28_Pos (28U)
4450#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
4451#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
4452#define CAN_F5R2_FB29_Pos (29U)
4453#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
4454#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
4455#define CAN_F5R2_FB30_Pos (30U)
4456#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
4457#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
4458#define CAN_F5R2_FB31_Pos (31U)
4459#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
4460#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
4462/******************* Bit definition for CAN_F6R2 register *******************/
4463#define CAN_F6R2_FB0_Pos (0U)
4464#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
4465#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
4466#define CAN_F6R2_FB1_Pos (1U)
4467#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
4468#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
4469#define CAN_F6R2_FB2_Pos (2U)
4470#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
4471#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
4472#define CAN_F6R2_FB3_Pos (3U)
4473#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
4474#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
4475#define CAN_F6R2_FB4_Pos (4U)
4476#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
4477#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
4478#define CAN_F6R2_FB5_Pos (5U)
4479#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
4480#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
4481#define CAN_F6R2_FB6_Pos (6U)
4482#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
4483#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
4484#define CAN_F6R2_FB7_Pos (7U)
4485#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
4486#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
4487#define CAN_F6R2_FB8_Pos (8U)
4488#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
4489#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
4490#define CAN_F6R2_FB9_Pos (9U)
4491#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
4492#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
4493#define CAN_F6R2_FB10_Pos (10U)
4494#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
4495#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
4496#define CAN_F6R2_FB11_Pos (11U)
4497#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
4498#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
4499#define CAN_F6R2_FB12_Pos (12U)
4500#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
4501#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
4502#define CAN_F6R2_FB13_Pos (13U)
4503#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
4504#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
4505#define CAN_F6R2_FB14_Pos (14U)
4506#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
4507#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
4508#define CAN_F6R2_FB15_Pos (15U)
4509#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
4510#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
4511#define CAN_F6R2_FB16_Pos (16U)
4512#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
4513#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
4514#define CAN_F6R2_FB17_Pos (17U)
4515#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
4516#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
4517#define CAN_F6R2_FB18_Pos (18U)
4518#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
4519#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
4520#define CAN_F6R2_FB19_Pos (19U)
4521#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
4522#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
4523#define CAN_F6R2_FB20_Pos (20U)
4524#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
4525#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
4526#define CAN_F6R2_FB21_Pos (21U)
4527#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
4528#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
4529#define CAN_F6R2_FB22_Pos (22U)
4530#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
4531#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
4532#define CAN_F6R2_FB23_Pos (23U)
4533#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
4534#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
4535#define CAN_F6R2_FB24_Pos (24U)
4536#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
4537#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
4538#define CAN_F6R2_FB25_Pos (25U)
4539#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
4540#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
4541#define CAN_F6R2_FB26_Pos (26U)
4542#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
4543#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
4544#define CAN_F6R2_FB27_Pos (27U)
4545#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
4546#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
4547#define CAN_F6R2_FB28_Pos (28U)
4548#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
4549#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
4550#define CAN_F6R2_FB29_Pos (29U)
4551#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
4552#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
4553#define CAN_F6R2_FB30_Pos (30U)
4554#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
4555#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
4556#define CAN_F6R2_FB31_Pos (31U)
4557#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
4558#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
4560/******************* Bit definition for CAN_F7R2 register *******************/
4561#define CAN_F7R2_FB0_Pos (0U)
4562#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
4563#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
4564#define CAN_F7R2_FB1_Pos (1U)
4565#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
4566#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
4567#define CAN_F7R2_FB2_Pos (2U)
4568#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
4569#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
4570#define CAN_F7R2_FB3_Pos (3U)
4571#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
4572#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
4573#define CAN_F7R2_FB4_Pos (4U)
4574#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
4575#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
4576#define CAN_F7R2_FB5_Pos (5U)
4577#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
4578#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
4579#define CAN_F7R2_FB6_Pos (6U)
4580#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
4581#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
4582#define CAN_F7R2_FB7_Pos (7U)
4583#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
4584#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
4585#define CAN_F7R2_FB8_Pos (8U)
4586#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
4587#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
4588#define CAN_F7R2_FB9_Pos (9U)
4589#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
4590#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
4591#define CAN_F7R2_FB10_Pos (10U)
4592#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
4593#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
4594#define CAN_F7R2_FB11_Pos (11U)
4595#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
4596#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
4597#define CAN_F7R2_FB12_Pos (12U)
4598#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
4599#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
4600#define CAN_F7R2_FB13_Pos (13U)
4601#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
4602#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
4603#define CAN_F7R2_FB14_Pos (14U)
4604#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
4605#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
4606#define CAN_F7R2_FB15_Pos (15U)
4607#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
4608#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
4609#define CAN_F7R2_FB16_Pos (16U)
4610#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
4611#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
4612#define CAN_F7R2_FB17_Pos (17U)
4613#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
4614#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
4615#define CAN_F7R2_FB18_Pos (18U)
4616#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
4617#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
4618#define CAN_F7R2_FB19_Pos (19U)
4619#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
4620#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
4621#define CAN_F7R2_FB20_Pos (20U)
4622#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
4623#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
4624#define CAN_F7R2_FB21_Pos (21U)
4625#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
4626#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
4627#define CAN_F7R2_FB22_Pos (22U)
4628#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
4629#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
4630#define CAN_F7R2_FB23_Pos (23U)
4631#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
4632#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
4633#define CAN_F7R2_FB24_Pos (24U)
4634#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
4635#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
4636#define CAN_F7R2_FB25_Pos (25U)
4637#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
4638#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
4639#define CAN_F7R2_FB26_Pos (26U)
4640#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
4641#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
4642#define CAN_F7R2_FB27_Pos (27U)
4643#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
4644#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
4645#define CAN_F7R2_FB28_Pos (28U)
4646#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
4647#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
4648#define CAN_F7R2_FB29_Pos (29U)
4649#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
4650#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
4651#define CAN_F7R2_FB30_Pos (30U)
4652#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
4653#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
4654#define CAN_F7R2_FB31_Pos (31U)
4655#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
4656#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
4658/******************* Bit definition for CAN_F8R2 register *******************/
4659#define CAN_F8R2_FB0_Pos (0U)
4660#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
4661#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
4662#define CAN_F8R2_FB1_Pos (1U)
4663#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
4664#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
4665#define CAN_F8R2_FB2_Pos (2U)
4666#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
4667#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
4668#define CAN_F8R2_FB3_Pos (3U)
4669#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
4670#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
4671#define CAN_F8R2_FB4_Pos (4U)
4672#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
4673#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
4674#define CAN_F8R2_FB5_Pos (5U)
4675#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
4676#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
4677#define CAN_F8R2_FB6_Pos (6U)
4678#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
4679#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
4680#define CAN_F8R2_FB7_Pos (7U)
4681#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
4682#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
4683#define CAN_F8R2_FB8_Pos (8U)
4684#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
4685#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
4686#define CAN_F8R2_FB9_Pos (9U)
4687#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
4688#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
4689#define CAN_F8R2_FB10_Pos (10U)
4690#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
4691#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
4692#define CAN_F8R2_FB11_Pos (11U)
4693#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
4694#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
4695#define CAN_F8R2_FB12_Pos (12U)
4696#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
4697#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
4698#define CAN_F8R2_FB13_Pos (13U)
4699#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
4700#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
4701#define CAN_F8R2_FB14_Pos (14U)
4702#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
4703#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
4704#define CAN_F8R2_FB15_Pos (15U)
4705#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
4706#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
4707#define CAN_F8R2_FB16_Pos (16U)
4708#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
4709#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
4710#define CAN_F8R2_FB17_Pos (17U)
4711#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
4712#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
4713#define CAN_F8R2_FB18_Pos (18U)
4714#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
4715#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
4716#define CAN_F8R2_FB19_Pos (19U)
4717#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
4718#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
4719#define CAN_F8R2_FB20_Pos (20U)
4720#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
4721#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
4722#define CAN_F8R2_FB21_Pos (21U)
4723#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
4724#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
4725#define CAN_F8R2_FB22_Pos (22U)
4726#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
4727#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
4728#define CAN_F8R2_FB23_Pos (23U)
4729#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
4730#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
4731#define CAN_F8R2_FB24_Pos (24U)
4732#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
4733#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
4734#define CAN_F8R2_FB25_Pos (25U)
4735#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
4736#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
4737#define CAN_F8R2_FB26_Pos (26U)
4738#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
4739#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
4740#define CAN_F8R2_FB27_Pos (27U)
4741#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
4742#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
4743#define CAN_F8R2_FB28_Pos (28U)
4744#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
4745#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
4746#define CAN_F8R2_FB29_Pos (29U)
4747#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
4748#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
4749#define CAN_F8R2_FB30_Pos (30U)
4750#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
4751#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
4752#define CAN_F8R2_FB31_Pos (31U)
4753#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
4754#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
4756/******************* Bit definition for CAN_F9R2 register *******************/
4757#define CAN_F9R2_FB0_Pos (0U)
4758#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
4759#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
4760#define CAN_F9R2_FB1_Pos (1U)
4761#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
4762#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
4763#define CAN_F9R2_FB2_Pos (2U)
4764#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
4765#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
4766#define CAN_F9R2_FB3_Pos (3U)
4767#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
4768#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
4769#define CAN_F9R2_FB4_Pos (4U)
4770#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
4771#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
4772#define CAN_F9R2_FB5_Pos (5U)
4773#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
4774#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
4775#define CAN_F9R2_FB6_Pos (6U)
4776#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
4777#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
4778#define CAN_F9R2_FB7_Pos (7U)
4779#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
4780#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
4781#define CAN_F9R2_FB8_Pos (8U)
4782#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
4783#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
4784#define CAN_F9R2_FB9_Pos (9U)
4785#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
4786#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
4787#define CAN_F9R2_FB10_Pos (10U)
4788#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
4789#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
4790#define CAN_F9R2_FB11_Pos (11U)
4791#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
4792#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
4793#define CAN_F9R2_FB12_Pos (12U)
4794#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
4795#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
4796#define CAN_F9R2_FB13_Pos (13U)
4797#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
4798#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
4799#define CAN_F9R2_FB14_Pos (14U)
4800#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
4801#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
4802#define CAN_F9R2_FB15_Pos (15U)
4803#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
4804#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
4805#define CAN_F9R2_FB16_Pos (16U)
4806#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
4807#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
4808#define CAN_F9R2_FB17_Pos (17U)
4809#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
4810#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
4811#define CAN_F9R2_FB18_Pos (18U)
4812#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
4813#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
4814#define CAN_F9R2_FB19_Pos (19U)
4815#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
4816#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
4817#define CAN_F9R2_FB20_Pos (20U)
4818#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
4819#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
4820#define CAN_F9R2_FB21_Pos (21U)
4821#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
4822#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
4823#define CAN_F9R2_FB22_Pos (22U)
4824#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
4825#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
4826#define CAN_F9R2_FB23_Pos (23U)
4827#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
4828#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
4829#define CAN_F9R2_FB24_Pos (24U)
4830#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
4831#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
4832#define CAN_F9R2_FB25_Pos (25U)
4833#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
4834#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
4835#define CAN_F9R2_FB26_Pos (26U)
4836#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
4837#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
4838#define CAN_F9R2_FB27_Pos (27U)
4839#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
4840#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
4841#define CAN_F9R2_FB28_Pos (28U)
4842#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
4843#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
4844#define CAN_F9R2_FB29_Pos (29U)
4845#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
4846#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
4847#define CAN_F9R2_FB30_Pos (30U)
4848#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
4849#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
4850#define CAN_F9R2_FB31_Pos (31U)
4851#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
4852#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
4854/******************* Bit definition for CAN_F10R2 register ******************/
4855#define CAN_F10R2_FB0_Pos (0U)
4856#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
4857#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
4858#define CAN_F10R2_FB1_Pos (1U)
4859#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
4860#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
4861#define CAN_F10R2_FB2_Pos (2U)
4862#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
4863#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
4864#define CAN_F10R2_FB3_Pos (3U)
4865#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
4866#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
4867#define CAN_F10R2_FB4_Pos (4U)
4868#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
4869#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
4870#define CAN_F10R2_FB5_Pos (5U)
4871#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
4872#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
4873#define CAN_F10R2_FB6_Pos (6U)
4874#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
4875#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
4876#define CAN_F10R2_FB7_Pos (7U)
4877#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
4878#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
4879#define CAN_F10R2_FB8_Pos (8U)
4880#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
4881#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
4882#define CAN_F10R2_FB9_Pos (9U)
4883#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
4884#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
4885#define CAN_F10R2_FB10_Pos (10U)
4886#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
4887#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
4888#define CAN_F10R2_FB11_Pos (11U)
4889#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
4890#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
4891#define CAN_F10R2_FB12_Pos (12U)
4892#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
4893#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
4894#define CAN_F10R2_FB13_Pos (13U)
4895#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
4896#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
4897#define CAN_F10R2_FB14_Pos (14U)
4898#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
4899#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
4900#define CAN_F10R2_FB15_Pos (15U)
4901#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
4902#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
4903#define CAN_F10R2_FB16_Pos (16U)
4904#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
4905#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
4906#define CAN_F10R2_FB17_Pos (17U)
4907#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
4908#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
4909#define CAN_F10R2_FB18_Pos (18U)
4910#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
4911#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
4912#define CAN_F10R2_FB19_Pos (19U)
4913#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
4914#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
4915#define CAN_F10R2_FB20_Pos (20U)
4916#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
4917#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
4918#define CAN_F10R2_FB21_Pos (21U)
4919#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
4920#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
4921#define CAN_F10R2_FB22_Pos (22U)
4922#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
4923#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
4924#define CAN_F10R2_FB23_Pos (23U)
4925#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
4926#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
4927#define CAN_F10R2_FB24_Pos (24U)
4928#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
4929#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
4930#define CAN_F10R2_FB25_Pos (25U)
4931#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
4932#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
4933#define CAN_F10R2_FB26_Pos (26U)
4934#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
4935#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
4936#define CAN_F10R2_FB27_Pos (27U)
4937#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
4938#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
4939#define CAN_F10R2_FB28_Pos (28U)
4940#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
4941#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
4942#define CAN_F10R2_FB29_Pos (29U)
4943#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
4944#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
4945#define CAN_F10R2_FB30_Pos (30U)
4946#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
4947#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
4948#define CAN_F10R2_FB31_Pos (31U)
4949#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
4950#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
4952/******************* Bit definition for CAN_F11R2 register ******************/
4953#define CAN_F11R2_FB0_Pos (0U)
4954#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
4955#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
4956#define CAN_F11R2_FB1_Pos (1U)
4957#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
4958#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
4959#define CAN_F11R2_FB2_Pos (2U)
4960#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
4961#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
4962#define CAN_F11R2_FB3_Pos (3U)
4963#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
4964#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
4965#define CAN_F11R2_FB4_Pos (4U)
4966#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
4967#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
4968#define CAN_F11R2_FB5_Pos (5U)
4969#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
4970#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
4971#define CAN_F11R2_FB6_Pos (6U)
4972#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
4973#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
4974#define CAN_F11R2_FB7_Pos (7U)
4975#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
4976#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
4977#define CAN_F11R2_FB8_Pos (8U)
4978#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
4979#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
4980#define CAN_F11R2_FB9_Pos (9U)
4981#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
4982#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
4983#define CAN_F11R2_FB10_Pos (10U)
4984#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
4985#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
4986#define CAN_F11R2_FB11_Pos (11U)
4987#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
4988#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
4989#define CAN_F11R2_FB12_Pos (12U)
4990#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
4991#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
4992#define CAN_F11R2_FB13_Pos (13U)
4993#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
4994#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
4995#define CAN_F11R2_FB14_Pos (14U)
4996#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
4997#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
4998#define CAN_F11R2_FB15_Pos (15U)
4999#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
5000#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
5001#define CAN_F11R2_FB16_Pos (16U)
5002#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
5003#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
5004#define CAN_F11R2_FB17_Pos (17U)
5005#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
5006#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
5007#define CAN_F11R2_FB18_Pos (18U)
5008#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
5009#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
5010#define CAN_F11R2_FB19_Pos (19U)
5011#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
5012#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
5013#define CAN_F11R2_FB20_Pos (20U)
5014#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
5015#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
5016#define CAN_F11R2_FB21_Pos (21U)
5017#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
5018#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
5019#define CAN_F11R2_FB22_Pos (22U)
5020#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
5021#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
5022#define CAN_F11R2_FB23_Pos (23U)
5023#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
5024#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
5025#define CAN_F11R2_FB24_Pos (24U)
5026#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
5027#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
5028#define CAN_F11R2_FB25_Pos (25U)
5029#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
5030#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
5031#define CAN_F11R2_FB26_Pos (26U)
5032#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
5033#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
5034#define CAN_F11R2_FB27_Pos (27U)
5035#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
5036#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
5037#define CAN_F11R2_FB28_Pos (28U)
5038#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
5039#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
5040#define CAN_F11R2_FB29_Pos (29U)
5041#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
5042#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
5043#define CAN_F11R2_FB30_Pos (30U)
5044#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
5045#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
5046#define CAN_F11R2_FB31_Pos (31U)
5047#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
5048#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
5050/******************* Bit definition for CAN_F12R2 register ******************/
5051#define CAN_F12R2_FB0_Pos (0U)
5052#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
5053#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
5054#define CAN_F12R2_FB1_Pos (1U)
5055#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
5056#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
5057#define CAN_F12R2_FB2_Pos (2U)
5058#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
5059#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
5060#define CAN_F12R2_FB3_Pos (3U)
5061#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
5062#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
5063#define CAN_F12R2_FB4_Pos (4U)
5064#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
5065#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
5066#define CAN_F12R2_FB5_Pos (5U)
5067#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
5068#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
5069#define CAN_F12R2_FB6_Pos (6U)
5070#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
5071#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
5072#define CAN_F12R2_FB7_Pos (7U)
5073#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
5074#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
5075#define CAN_F12R2_FB8_Pos (8U)
5076#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
5077#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
5078#define CAN_F12R2_FB9_Pos (9U)
5079#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
5080#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
5081#define CAN_F12R2_FB10_Pos (10U)
5082#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
5083#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
5084#define CAN_F12R2_FB11_Pos (11U)
5085#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
5086#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
5087#define CAN_F12R2_FB12_Pos (12U)
5088#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
5089#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
5090#define CAN_F12R2_FB13_Pos (13U)
5091#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
5092#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
5093#define CAN_F12R2_FB14_Pos (14U)
5094#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
5095#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
5096#define CAN_F12R2_FB15_Pos (15U)
5097#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
5098#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
5099#define CAN_F12R2_FB16_Pos (16U)
5100#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
5101#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
5102#define CAN_F12R2_FB17_Pos (17U)
5103#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
5104#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
5105#define CAN_F12R2_FB18_Pos (18U)
5106#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
5107#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
5108#define CAN_F12R2_FB19_Pos (19U)
5109#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
5110#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
5111#define CAN_F12R2_FB20_Pos (20U)
5112#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
5113#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
5114#define CAN_F12R2_FB21_Pos (21U)
5115#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
5116#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
5117#define CAN_F12R2_FB22_Pos (22U)
5118#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
5119#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
5120#define CAN_F12R2_FB23_Pos (23U)
5121#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
5122#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
5123#define CAN_F12R2_FB24_Pos (24U)
5124#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
5125#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
5126#define CAN_F12R2_FB25_Pos (25U)
5127#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
5128#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
5129#define CAN_F12R2_FB26_Pos (26U)
5130#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
5131#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
5132#define CAN_F12R2_FB27_Pos (27U)
5133#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
5134#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
5135#define CAN_F12R2_FB28_Pos (28U)
5136#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
5137#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
5138#define CAN_F12R2_FB29_Pos (29U)
5139#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
5140#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
5141#define CAN_F12R2_FB30_Pos (30U)
5142#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
5143#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
5144#define CAN_F12R2_FB31_Pos (31U)
5145#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
5146#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
5148/******************* Bit definition for CAN_F13R2 register ******************/
5149#define CAN_F13R2_FB0_Pos (0U)
5150#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
5151#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
5152#define CAN_F13R2_FB1_Pos (1U)
5153#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
5154#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
5155#define CAN_F13R2_FB2_Pos (2U)
5156#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
5157#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
5158#define CAN_F13R2_FB3_Pos (3U)
5159#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
5160#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
5161#define CAN_F13R2_FB4_Pos (4U)
5162#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
5163#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
5164#define CAN_F13R2_FB5_Pos (5U)
5165#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
5166#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
5167#define CAN_F13R2_FB6_Pos (6U)
5168#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
5169#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
5170#define CAN_F13R2_FB7_Pos (7U)
5171#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
5172#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
5173#define CAN_F13R2_FB8_Pos (8U)
5174#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
5175#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
5176#define CAN_F13R2_FB9_Pos (9U)
5177#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
5178#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
5179#define CAN_F13R2_FB10_Pos (10U)
5180#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
5181#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
5182#define CAN_F13R2_FB11_Pos (11U)
5183#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
5184#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
5185#define CAN_F13R2_FB12_Pos (12U)
5186#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
5187#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
5188#define CAN_F13R2_FB13_Pos (13U)
5189#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
5190#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
5191#define CAN_F13R2_FB14_Pos (14U)
5192#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
5193#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
5194#define CAN_F13R2_FB15_Pos (15U)
5195#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
5196#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
5197#define CAN_F13R2_FB16_Pos (16U)
5198#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
5199#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
5200#define CAN_F13R2_FB17_Pos (17U)
5201#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
5202#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
5203#define CAN_F13R2_FB18_Pos (18U)
5204#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
5205#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
5206#define CAN_F13R2_FB19_Pos (19U)
5207#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
5208#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
5209#define CAN_F13R2_FB20_Pos (20U)
5210#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
5211#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
5212#define CAN_F13R2_FB21_Pos (21U)
5213#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
5214#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
5215#define CAN_F13R2_FB22_Pos (22U)
5216#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
5217#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
5218#define CAN_F13R2_FB23_Pos (23U)
5219#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
5220#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
5221#define CAN_F13R2_FB24_Pos (24U)
5222#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
5223#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
5224#define CAN_F13R2_FB25_Pos (25U)
5225#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
5226#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
5227#define CAN_F13R2_FB26_Pos (26U)
5228#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
5229#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
5230#define CAN_F13R2_FB27_Pos (27U)
5231#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
5232#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
5233#define CAN_F13R2_FB28_Pos (28U)
5234#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
5235#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
5236#define CAN_F13R2_FB29_Pos (29U)
5237#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
5238#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
5239#define CAN_F13R2_FB30_Pos (30U)
5240#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
5241#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
5242#define CAN_F13R2_FB31_Pos (31U)
5243#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
5244#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
5247/******************************************************************************/
5248/* */
5249/* CRC calculation unit */
5250/* */
5251/******************************************************************************/
5252/******************* Bit definition for CRC_DR register *********************/
5253#define CRC_DR_DR_Pos (0U)
5254#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5255#define CRC_DR_DR CRC_DR_DR_Msk
5257/******************* Bit definition for CRC_IDR register ********************/
5258#define CRC_IDR_IDR_Pos (0U)
5259#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
5260#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5262/******************** Bit definition for CRC_CR register ********************/
5263#define CRC_CR_RESET_Pos (0U)
5264#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5265#define CRC_CR_RESET CRC_CR_RESET_Msk
5266#define CRC_CR_POLYSIZE_Pos (3U)
5267#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
5268#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
5269#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
5270#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
5271#define CRC_CR_REV_IN_Pos (5U)
5272#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
5273#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
5274#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
5275#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
5276#define CRC_CR_REV_OUT_Pos (7U)
5277#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
5278#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
5280/******************* Bit definition for CRC_INIT register *******************/
5281#define CRC_INIT_INIT_Pos (0U)
5282#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
5283#define CRC_INIT_INIT CRC_INIT_INIT_Msk
5285/******************* Bit definition for CRC_POL register ********************/
5286#define CRC_POL_POL_Pos (0U)
5287#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
5288#define CRC_POL_POL CRC_POL_POL_Msk
5291/******************************************************************************/
5292/* */
5293/* Digital to Analog Converter */
5294/* */
5295/******************************************************************************/
5296/******************** Bit definition for DAC_CR register ********************/
5297#define DAC_CR_EN1_Pos (0U)
5298#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5299#define DAC_CR_EN1 DAC_CR_EN1_Msk
5300#define DAC_CR_BOFF1_Pos (1U)
5301#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)
5302#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk
5303#define DAC_CR_TEN1_Pos (2U)
5304#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5305#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5306#define DAC_CR_TSEL1_Pos (3U)
5307#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)
5308#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5309#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5310#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5311#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5312#define DAC_CR_WAVE1_Pos (6U)
5313#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5314#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5315#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5316#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5317#define DAC_CR_MAMP1_Pos (8U)
5318#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5319#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5320#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5321#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5322#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5323#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5324#define DAC_CR_DMAEN1_Pos (12U)
5325#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5326#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5327#define DAC_CR_DMAUDRIE1_Pos (13U)
5328#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5329#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5330#define DAC_CR_EN2_Pos (16U)
5331#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5332#define DAC_CR_EN2 DAC_CR_EN2_Msk
5333#define DAC_CR_BOFF2_Pos (17U)
5334#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)
5335#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk
5336#define DAC_CR_TEN2_Pos (18U)
5337#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5338#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5339#define DAC_CR_TSEL2_Pos (19U)
5340#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)
5341#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5342#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5343#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5344#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5345#define DAC_CR_WAVE2_Pos (22U)
5346#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5347#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5348#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5349#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5350#define DAC_CR_MAMP2_Pos (24U)
5351#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5352#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5353#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5354#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5355#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5356#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5357#define DAC_CR_DMAEN2_Pos (28U)
5358#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5359#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5360#define DAC_CR_DMAUDRIE2_Pos (29U)
5361#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5362#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5364/***************** Bit definition for DAC_SWTRIGR register ******************/
5365#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5366#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5367#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5368#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5369#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5370#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5372/***************** Bit definition for DAC_DHR12R1 register ******************/
5373#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5374#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5375#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5377/***************** Bit definition for DAC_DHR12L1 register ******************/
5378#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5379#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5380#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5382/****************** Bit definition for DAC_DHR8R1 register ******************/
5383#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5384#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5385#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5387/***************** Bit definition for DAC_DHR12R2 register ******************/
5388#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5389#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5390#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5392/***************** Bit definition for DAC_DHR12L2 register ******************/
5393#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5394#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5395#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5397/****************** Bit definition for DAC_DHR8R2 register ******************/
5398#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5399#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5400#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5402/***************** Bit definition for DAC_DHR12RD register ******************/
5403#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5404#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5405#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5406#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5407#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5408#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5410/***************** Bit definition for DAC_DHR12LD register ******************/
5411#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5412#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5413#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5414#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5415#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5416#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5418/****************** Bit definition for DAC_DHR8RD register ******************/
5419#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5420#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5421#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5422#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5423#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5424#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5426/******************* Bit definition for DAC_DOR1 register *******************/
5427#define DAC_DOR1_DACC1DOR_Pos (0U)
5428#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5429#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5431/******************* Bit definition for DAC_DOR2 register *******************/
5432#define DAC_DOR2_DACC2DOR_Pos (0U)
5433#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5434#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5436/******************** Bit definition for DAC_SR register ********************/
5437#define DAC_SR_DMAUDR1_Pos (13U)
5438#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5439#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5440#define DAC_SR_DMAUDR2_Pos (29U)
5441#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5442#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5445/******************************************************************************/
5446/* */
5447/* Debug MCU */
5448/* */
5449/******************************************************************************/
5450
5451
5452/******************************************************************************/
5453/* */
5454/* DMA Controller */
5455/* */
5456/******************************************************************************/
5457/******************** Bits definition for DMA_SxCR register *****************/
5458#define DMA_SxCR_CHSEL_Pos (25U)
5459#define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos)
5460#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
5461#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos)
5462#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos)
5463#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos)
5464#define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos)
5465#define DMA_SxCR_MBURST_Pos (23U)
5466#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
5467#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
5468#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
5469#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
5470#define DMA_SxCR_PBURST_Pos (21U)
5471#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
5472#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
5473#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
5474#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
5475#define DMA_SxCR_CT_Pos (19U)
5476#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
5477#define DMA_SxCR_CT DMA_SxCR_CT_Msk
5478#define DMA_SxCR_DBM_Pos (18U)
5479#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
5480#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
5481#define DMA_SxCR_PL_Pos (16U)
5482#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
5483#define DMA_SxCR_PL DMA_SxCR_PL_Msk
5484#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
5485#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
5486#define DMA_SxCR_PINCOS_Pos (15U)
5487#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
5488#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
5489#define DMA_SxCR_MSIZE_Pos (13U)
5490#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
5491#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
5492#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
5493#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
5494#define DMA_SxCR_PSIZE_Pos (11U)
5495#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
5496#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
5497#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
5498#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
5499#define DMA_SxCR_MINC_Pos (10U)
5500#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
5501#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
5502#define DMA_SxCR_PINC_Pos (9U)
5503#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
5504#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
5505#define DMA_SxCR_CIRC_Pos (8U)
5506#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
5507#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
5508#define DMA_SxCR_DIR_Pos (6U)
5509#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
5510#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
5511#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
5512#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
5513#define DMA_SxCR_PFCTRL_Pos (5U)
5514#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
5515#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
5516#define DMA_SxCR_TCIE_Pos (4U)
5517#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
5518#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
5519#define DMA_SxCR_HTIE_Pos (3U)
5520#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
5521#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
5522#define DMA_SxCR_TEIE_Pos (2U)
5523#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
5524#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
5525#define DMA_SxCR_DMEIE_Pos (1U)
5526#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
5527#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
5528#define DMA_SxCR_EN_Pos (0U)
5529#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
5530#define DMA_SxCR_EN DMA_SxCR_EN_Msk
5531
5532/******************** Bits definition for DMA_SxCNDTR register **************/
5533#define DMA_SxNDT_Pos (0U)
5534#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
5535#define DMA_SxNDT DMA_SxNDT_Msk
5536#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
5537#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
5538#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
5539#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
5540#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
5541#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
5542#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
5543#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
5544#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
5545#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
5546#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
5547#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
5548#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
5549#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
5550#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
5551#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
5553/******************** Bits definition for DMA_SxFCR register ****************/
5554#define DMA_SxFCR_FEIE_Pos (7U)
5555#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
5556#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
5557#define DMA_SxFCR_FS_Pos (3U)
5558#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
5559#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
5560#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
5561#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
5562#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
5563#define DMA_SxFCR_DMDIS_Pos (2U)
5564#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
5565#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
5566#define DMA_SxFCR_FTH_Pos (0U)
5567#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
5568#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
5569#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
5570#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
5572/******************** Bits definition for DMA_LISR register *****************/
5573#define DMA_LISR_TCIF3_Pos (27U)
5574#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
5575#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
5576#define DMA_LISR_HTIF3_Pos (26U)
5577#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
5578#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
5579#define DMA_LISR_TEIF3_Pos (25U)
5580#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
5581#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
5582#define DMA_LISR_DMEIF3_Pos (24U)
5583#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
5584#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
5585#define DMA_LISR_FEIF3_Pos (22U)
5586#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
5587#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
5588#define DMA_LISR_TCIF2_Pos (21U)
5589#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
5590#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
5591#define DMA_LISR_HTIF2_Pos (20U)
5592#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
5593#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
5594#define DMA_LISR_TEIF2_Pos (19U)
5595#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
5596#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
5597#define DMA_LISR_DMEIF2_Pos (18U)
5598#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
5599#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
5600#define DMA_LISR_FEIF2_Pos (16U)
5601#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
5602#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
5603#define DMA_LISR_TCIF1_Pos (11U)
5604#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
5605#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
5606#define DMA_LISR_HTIF1_Pos (10U)
5607#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
5608#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
5609#define DMA_LISR_TEIF1_Pos (9U)
5610#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
5611#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
5612#define DMA_LISR_DMEIF1_Pos (8U)
5613#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
5614#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
5615#define DMA_LISR_FEIF1_Pos (6U)
5616#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
5617#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
5618#define DMA_LISR_TCIF0_Pos (5U)
5619#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
5620#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
5621#define DMA_LISR_HTIF0_Pos (4U)
5622#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
5623#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
5624#define DMA_LISR_TEIF0_Pos (3U)
5625#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
5626#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
5627#define DMA_LISR_DMEIF0_Pos (2U)
5628#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
5629#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
5630#define DMA_LISR_FEIF0_Pos (0U)
5631#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
5632#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
5633
5634/******************** Bits definition for DMA_HISR register *****************/
5635#define DMA_HISR_TCIF7_Pos (27U)
5636#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
5637#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
5638#define DMA_HISR_HTIF7_Pos (26U)
5639#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
5640#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
5641#define DMA_HISR_TEIF7_Pos (25U)
5642#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
5643#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
5644#define DMA_HISR_DMEIF7_Pos (24U)
5645#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
5646#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
5647#define DMA_HISR_FEIF7_Pos (22U)
5648#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
5649#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
5650#define DMA_HISR_TCIF6_Pos (21U)
5651#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
5652#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
5653#define DMA_HISR_HTIF6_Pos (20U)
5654#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
5655#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
5656#define DMA_HISR_TEIF6_Pos (19U)
5657#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
5658#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
5659#define DMA_HISR_DMEIF6_Pos (18U)
5660#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
5661#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
5662#define DMA_HISR_FEIF6_Pos (16U)
5663#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
5664#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
5665#define DMA_HISR_TCIF5_Pos (11U)
5666#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
5667#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
5668#define DMA_HISR_HTIF5_Pos (10U)
5669#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
5670#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
5671#define DMA_HISR_TEIF5_Pos (9U)
5672#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
5673#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
5674#define DMA_HISR_DMEIF5_Pos (8U)
5675#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
5676#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
5677#define DMA_HISR_FEIF5_Pos (6U)
5678#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
5679#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
5680#define DMA_HISR_TCIF4_Pos (5U)
5681#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
5682#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
5683#define DMA_HISR_HTIF4_Pos (4U)
5684#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
5685#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
5686#define DMA_HISR_TEIF4_Pos (3U)
5687#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
5688#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
5689#define DMA_HISR_DMEIF4_Pos (2U)
5690#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
5691#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
5692#define DMA_HISR_FEIF4_Pos (0U)
5693#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
5694#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
5695
5696/******************** Bits definition for DMA_LIFCR register ****************/
5697#define DMA_LIFCR_CTCIF3_Pos (27U)
5698#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
5699#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
5700#define DMA_LIFCR_CHTIF3_Pos (26U)
5701#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
5702#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
5703#define DMA_LIFCR_CTEIF3_Pos (25U)
5704#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
5705#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
5706#define DMA_LIFCR_CDMEIF3_Pos (24U)
5707#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
5708#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
5709#define DMA_LIFCR_CFEIF3_Pos (22U)
5710#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
5711#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
5712#define DMA_LIFCR_CTCIF2_Pos (21U)
5713#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
5714#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
5715#define DMA_LIFCR_CHTIF2_Pos (20U)
5716#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
5717#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
5718#define DMA_LIFCR_CTEIF2_Pos (19U)
5719#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
5720#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
5721#define DMA_LIFCR_CDMEIF2_Pos (18U)
5722#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
5723#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
5724#define DMA_LIFCR_CFEIF2_Pos (16U)
5725#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
5726#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
5727#define DMA_LIFCR_CTCIF1_Pos (11U)
5728#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
5729#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
5730#define DMA_LIFCR_CHTIF1_Pos (10U)
5731#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
5732#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
5733#define DMA_LIFCR_CTEIF1_Pos (9U)
5734#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
5735#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
5736#define DMA_LIFCR_CDMEIF1_Pos (8U)
5737#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
5738#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
5739#define DMA_LIFCR_CFEIF1_Pos (6U)
5740#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
5741#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
5742#define DMA_LIFCR_CTCIF0_Pos (5U)
5743#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
5744#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
5745#define DMA_LIFCR_CHTIF0_Pos (4U)
5746#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
5747#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
5748#define DMA_LIFCR_CTEIF0_Pos (3U)
5749#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
5750#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
5751#define DMA_LIFCR_CDMEIF0_Pos (2U)
5752#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
5753#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
5754#define DMA_LIFCR_CFEIF0_Pos (0U)
5755#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
5756#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
5757
5758/******************** Bits definition for DMA_HIFCR register ****************/
5759#define DMA_HIFCR_CTCIF7_Pos (27U)
5760#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
5761#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
5762#define DMA_HIFCR_CHTIF7_Pos (26U)
5763#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
5764#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
5765#define DMA_HIFCR_CTEIF7_Pos (25U)
5766#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
5767#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
5768#define DMA_HIFCR_CDMEIF7_Pos (24U)
5769#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
5770#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
5771#define DMA_HIFCR_CFEIF7_Pos (22U)
5772#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
5773#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
5774#define DMA_HIFCR_CTCIF6_Pos (21U)
5775#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
5776#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
5777#define DMA_HIFCR_CHTIF6_Pos (20U)
5778#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
5779#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
5780#define DMA_HIFCR_CTEIF6_Pos (19U)
5781#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
5782#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
5783#define DMA_HIFCR_CDMEIF6_Pos (18U)
5784#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
5785#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
5786#define DMA_HIFCR_CFEIF6_Pos (16U)
5787#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
5788#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
5789#define DMA_HIFCR_CTCIF5_Pos (11U)
5790#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
5791#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
5792#define DMA_HIFCR_CHTIF5_Pos (10U)
5793#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
5794#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
5795#define DMA_HIFCR_CTEIF5_Pos (9U)
5796#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
5797#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
5798#define DMA_HIFCR_CDMEIF5_Pos (8U)
5799#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
5800#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
5801#define DMA_HIFCR_CFEIF5_Pos (6U)
5802#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
5803#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
5804#define DMA_HIFCR_CTCIF4_Pos (5U)
5805#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
5806#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
5807#define DMA_HIFCR_CHTIF4_Pos (4U)
5808#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
5809#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
5810#define DMA_HIFCR_CTEIF4_Pos (3U)
5811#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
5812#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
5813#define DMA_HIFCR_CDMEIF4_Pos (2U)
5814#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
5815#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
5816#define DMA_HIFCR_CFEIF4_Pos (0U)
5817#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
5818#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
5819
5820/****************** Bit definition for DMA_SxPAR register ********************/
5821#define DMA_SxPAR_PA_Pos (0U)
5822#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
5823#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
5825/****************** Bit definition for DMA_SxM0AR register ********************/
5826#define DMA_SxM0AR_M0A_Pos (0U)
5827#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
5828#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
5830/****************** Bit definition for DMA_SxM1AR register ********************/
5831#define DMA_SxM1AR_M1A_Pos (0U)
5832#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
5833#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
5836/******************************************************************************/
5837/* */
5838/* External Interrupt/Event Controller */
5839/* */
5840/******************************************************************************/
5841/******************* Bit definition for EXTI_IMR register *******************/
5842#define EXTI_IMR_MR0_Pos (0U)
5843#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
5844#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
5845#define EXTI_IMR_MR1_Pos (1U)
5846#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
5847#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
5848#define EXTI_IMR_MR2_Pos (2U)
5849#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
5850#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
5851#define EXTI_IMR_MR3_Pos (3U)
5852#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
5853#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
5854#define EXTI_IMR_MR4_Pos (4U)
5855#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
5856#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
5857#define EXTI_IMR_MR5_Pos (5U)
5858#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
5859#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
5860#define EXTI_IMR_MR6_Pos (6U)
5861#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
5862#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
5863#define EXTI_IMR_MR7_Pos (7U)
5864#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
5865#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
5866#define EXTI_IMR_MR8_Pos (8U)
5867#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
5868#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
5869#define EXTI_IMR_MR9_Pos (9U)
5870#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
5871#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
5872#define EXTI_IMR_MR10_Pos (10U)
5873#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
5874#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
5875#define EXTI_IMR_MR11_Pos (11U)
5876#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
5877#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
5878#define EXTI_IMR_MR12_Pos (12U)
5879#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
5880#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
5881#define EXTI_IMR_MR13_Pos (13U)
5882#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
5883#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
5884#define EXTI_IMR_MR14_Pos (14U)
5885#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
5886#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
5887#define EXTI_IMR_MR15_Pos (15U)
5888#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
5889#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
5890#define EXTI_IMR_MR16_Pos (16U)
5891#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
5892#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
5893#define EXTI_IMR_MR17_Pos (17U)
5894#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
5895#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
5896#define EXTI_IMR_MR18_Pos (18U)
5897#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
5898#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
5899#define EXTI_IMR_MR19_Pos (19U)
5900#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)
5901#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk
5902#define EXTI_IMR_MR20_Pos (20U)
5903#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos)
5904#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk
5905#define EXTI_IMR_MR21_Pos (21U)
5906#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos)
5907#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk
5908#define EXTI_IMR_MR22_Pos (22U)
5909#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos)
5910#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk
5911#define EXTI_IMR_MR23_Pos (23U)
5912#define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos)
5913#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk
5915/* Reference Defines */
5916#define EXTI_IMR_IM0 EXTI_IMR_MR0
5917#define EXTI_IMR_IM1 EXTI_IMR_MR1
5918#define EXTI_IMR_IM2 EXTI_IMR_MR2
5919#define EXTI_IMR_IM3 EXTI_IMR_MR3
5920#define EXTI_IMR_IM4 EXTI_IMR_MR4
5921#define EXTI_IMR_IM5 EXTI_IMR_MR5
5922#define EXTI_IMR_IM6 EXTI_IMR_MR6
5923#define EXTI_IMR_IM7 EXTI_IMR_MR7
5924#define EXTI_IMR_IM8 EXTI_IMR_MR8
5925#define EXTI_IMR_IM9 EXTI_IMR_MR9
5926#define EXTI_IMR_IM10 EXTI_IMR_MR10
5927#define EXTI_IMR_IM11 EXTI_IMR_MR11
5928#define EXTI_IMR_IM12 EXTI_IMR_MR12
5929#define EXTI_IMR_IM13 EXTI_IMR_MR13
5930#define EXTI_IMR_IM14 EXTI_IMR_MR14
5931#define EXTI_IMR_IM15 EXTI_IMR_MR15
5932#define EXTI_IMR_IM16 EXTI_IMR_MR16
5933#define EXTI_IMR_IM17 EXTI_IMR_MR17
5934#define EXTI_IMR_IM18 EXTI_IMR_MR18
5935#define EXTI_IMR_IM19 EXTI_IMR_MR19
5936#define EXTI_IMR_IM20 EXTI_IMR_MR20
5937#define EXTI_IMR_IM21 EXTI_IMR_MR21
5938#define EXTI_IMR_IM22 EXTI_IMR_MR22
5939#define EXTI_IMR_IM23 EXTI_IMR_MR23
5940
5941#define EXTI_IMR_IM_Pos (0U)
5942#define EXTI_IMR_IM_Msk (0xFFFFFFUL << EXTI_IMR_IM_Pos)
5943#define EXTI_IMR_IM EXTI_IMR_IM_Msk
5945/******************* Bit definition for EXTI_EMR register *******************/
5946#define EXTI_EMR_MR0_Pos (0U)
5947#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
5948#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
5949#define EXTI_EMR_MR1_Pos (1U)
5950#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
5951#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
5952#define EXTI_EMR_MR2_Pos (2U)
5953#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
5954#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
5955#define EXTI_EMR_MR3_Pos (3U)
5956#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
5957#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
5958#define EXTI_EMR_MR4_Pos (4U)
5959#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
5960#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
5961#define EXTI_EMR_MR5_Pos (5U)
5962#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
5963#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
5964#define EXTI_EMR_MR6_Pos (6U)
5965#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
5966#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
5967#define EXTI_EMR_MR7_Pos (7U)
5968#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
5969#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
5970#define EXTI_EMR_MR8_Pos (8U)
5971#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
5972#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
5973#define EXTI_EMR_MR9_Pos (9U)
5974#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
5975#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
5976#define EXTI_EMR_MR10_Pos (10U)
5977#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
5978#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
5979#define EXTI_EMR_MR11_Pos (11U)
5980#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
5981#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
5982#define EXTI_EMR_MR12_Pos (12U)
5983#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
5984#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
5985#define EXTI_EMR_MR13_Pos (13U)
5986#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
5987#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
5988#define EXTI_EMR_MR14_Pos (14U)
5989#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
5990#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
5991#define EXTI_EMR_MR15_Pos (15U)
5992#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
5993#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
5994#define EXTI_EMR_MR16_Pos (16U)
5995#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
5996#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
5997#define EXTI_EMR_MR17_Pos (17U)
5998#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
5999#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
6000#define EXTI_EMR_MR18_Pos (18U)
6001#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
6002#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
6003#define EXTI_EMR_MR19_Pos (19U)
6004#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)
6005#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk
6006#define EXTI_EMR_MR20_Pos (20U)
6007#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos)
6008#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk
6009#define EXTI_EMR_MR21_Pos (21U)
6010#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos)
6011#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk
6012#define EXTI_EMR_MR22_Pos (22U)
6013#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos)
6014#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk
6015#define EXTI_EMR_MR23_Pos (23U)
6016#define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos)
6017#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk
6019/* Reference Defines */
6020#define EXTI_EMR_EM0 EXTI_EMR_MR0
6021#define EXTI_EMR_EM1 EXTI_EMR_MR1
6022#define EXTI_EMR_EM2 EXTI_EMR_MR2
6023#define EXTI_EMR_EM3 EXTI_EMR_MR3
6024#define EXTI_EMR_EM4 EXTI_EMR_MR4
6025#define EXTI_EMR_EM5 EXTI_EMR_MR5
6026#define EXTI_EMR_EM6 EXTI_EMR_MR6
6027#define EXTI_EMR_EM7 EXTI_EMR_MR7
6028#define EXTI_EMR_EM8 EXTI_EMR_MR8
6029#define EXTI_EMR_EM9 EXTI_EMR_MR9
6030#define EXTI_EMR_EM10 EXTI_EMR_MR10
6031#define EXTI_EMR_EM11 EXTI_EMR_MR11
6032#define EXTI_EMR_EM12 EXTI_EMR_MR12
6033#define EXTI_EMR_EM13 EXTI_EMR_MR13
6034#define EXTI_EMR_EM14 EXTI_EMR_MR14
6035#define EXTI_EMR_EM15 EXTI_EMR_MR15
6036#define EXTI_EMR_EM16 EXTI_EMR_MR16
6037#define EXTI_EMR_EM17 EXTI_EMR_MR17
6038#define EXTI_EMR_EM18 EXTI_EMR_MR18
6039#define EXTI_EMR_EM19 EXTI_EMR_MR19
6040#define EXTI_EMR_EM20 EXTI_EMR_MR20
6041#define EXTI_EMR_EM21 EXTI_EMR_MR21
6042#define EXTI_EMR_EM22 EXTI_EMR_MR22
6043#define EXTI_EMR_EM23 EXTI_EMR_MR23
6044
6045
6046/****************** Bit definition for EXTI_RTSR register *******************/
6047#define EXTI_RTSR_TR0_Pos (0U)
6048#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
6049#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
6050#define EXTI_RTSR_TR1_Pos (1U)
6051#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
6052#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
6053#define EXTI_RTSR_TR2_Pos (2U)
6054#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
6055#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
6056#define EXTI_RTSR_TR3_Pos (3U)
6057#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
6058#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
6059#define EXTI_RTSR_TR4_Pos (4U)
6060#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
6061#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
6062#define EXTI_RTSR_TR5_Pos (5U)
6063#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
6064#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
6065#define EXTI_RTSR_TR6_Pos (6U)
6066#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
6067#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
6068#define EXTI_RTSR_TR7_Pos (7U)
6069#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
6070#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
6071#define EXTI_RTSR_TR8_Pos (8U)
6072#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
6073#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
6074#define EXTI_RTSR_TR9_Pos (9U)
6075#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
6076#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
6077#define EXTI_RTSR_TR10_Pos (10U)
6078#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
6079#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
6080#define EXTI_RTSR_TR11_Pos (11U)
6081#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
6082#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
6083#define EXTI_RTSR_TR12_Pos (12U)
6084#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
6085#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
6086#define EXTI_RTSR_TR13_Pos (13U)
6087#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
6088#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
6089#define EXTI_RTSR_TR14_Pos (14U)
6090#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
6091#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
6092#define EXTI_RTSR_TR15_Pos (15U)
6093#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
6094#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
6095#define EXTI_RTSR_TR16_Pos (16U)
6096#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
6097#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
6098#define EXTI_RTSR_TR17_Pos (17U)
6099#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
6100#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
6101#define EXTI_RTSR_TR18_Pos (18U)
6102#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
6103#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
6104#define EXTI_RTSR_TR19_Pos (19U)
6105#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)
6106#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk
6107#define EXTI_RTSR_TR20_Pos (20U)
6108#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos)
6109#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk
6110#define EXTI_RTSR_TR21_Pos (21U)
6111#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos)
6112#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk
6113#define EXTI_RTSR_TR22_Pos (22U)
6114#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos)
6115#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk
6116#define EXTI_RTSR_TR23_Pos (23U)
6117#define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos)
6118#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk
6120/****************** Bit definition for EXTI_FTSR register *******************/
6121#define EXTI_FTSR_TR0_Pos (0U)
6122#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
6123#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
6124#define EXTI_FTSR_TR1_Pos (1U)
6125#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
6126#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
6127#define EXTI_FTSR_TR2_Pos (2U)
6128#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
6129#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
6130#define EXTI_FTSR_TR3_Pos (3U)
6131#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
6132#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
6133#define EXTI_FTSR_TR4_Pos (4U)
6134#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
6135#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
6136#define EXTI_FTSR_TR5_Pos (5U)
6137#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
6138#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
6139#define EXTI_FTSR_TR6_Pos (6U)
6140#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
6141#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
6142#define EXTI_FTSR_TR7_Pos (7U)
6143#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
6144#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
6145#define EXTI_FTSR_TR8_Pos (8U)
6146#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
6147#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
6148#define EXTI_FTSR_TR9_Pos (9U)
6149#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
6150#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
6151#define EXTI_FTSR_TR10_Pos (10U)
6152#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
6153#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
6154#define EXTI_FTSR_TR11_Pos (11U)
6155#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
6156#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
6157#define EXTI_FTSR_TR12_Pos (12U)
6158#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
6159#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
6160#define EXTI_FTSR_TR13_Pos (13U)
6161#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
6162#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
6163#define EXTI_FTSR_TR14_Pos (14U)
6164#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
6165#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
6166#define EXTI_FTSR_TR15_Pos (15U)
6167#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
6168#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
6169#define EXTI_FTSR_TR16_Pos (16U)
6170#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
6171#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
6172#define EXTI_FTSR_TR17_Pos (17U)
6173#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
6174#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
6175#define EXTI_FTSR_TR18_Pos (18U)
6176#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
6177#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
6178#define EXTI_FTSR_TR19_Pos (19U)
6179#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)
6180#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk
6181#define EXTI_FTSR_TR20_Pos (20U)
6182#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos)
6183#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk
6184#define EXTI_FTSR_TR21_Pos (21U)
6185#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos)
6186#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk
6187#define EXTI_FTSR_TR22_Pos (22U)
6188#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos)
6189#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk
6190#define EXTI_FTSR_TR23_Pos (23U)
6191#define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos)
6192#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk
6194/****************** Bit definition for EXTI_SWIER register ******************/
6195#define EXTI_SWIER_SWIER0_Pos (0U)
6196#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
6197#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
6198#define EXTI_SWIER_SWIER1_Pos (1U)
6199#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
6200#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
6201#define EXTI_SWIER_SWIER2_Pos (2U)
6202#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
6203#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
6204#define EXTI_SWIER_SWIER3_Pos (3U)
6205#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
6206#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
6207#define EXTI_SWIER_SWIER4_Pos (4U)
6208#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
6209#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
6210#define EXTI_SWIER_SWIER5_Pos (5U)
6211#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
6212#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
6213#define EXTI_SWIER_SWIER6_Pos (6U)
6214#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
6215#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
6216#define EXTI_SWIER_SWIER7_Pos (7U)
6217#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
6218#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
6219#define EXTI_SWIER_SWIER8_Pos (8U)
6220#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
6221#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
6222#define EXTI_SWIER_SWIER9_Pos (9U)
6223#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
6224#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
6225#define EXTI_SWIER_SWIER10_Pos (10U)
6226#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
6227#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
6228#define EXTI_SWIER_SWIER11_Pos (11U)
6229#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
6230#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
6231#define EXTI_SWIER_SWIER12_Pos (12U)
6232#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
6233#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
6234#define EXTI_SWIER_SWIER13_Pos (13U)
6235#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
6236#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
6237#define EXTI_SWIER_SWIER14_Pos (14U)
6238#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
6239#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
6240#define EXTI_SWIER_SWIER15_Pos (15U)
6241#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
6242#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
6243#define EXTI_SWIER_SWIER16_Pos (16U)
6244#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
6245#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
6246#define EXTI_SWIER_SWIER17_Pos (17U)
6247#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
6248#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
6249#define EXTI_SWIER_SWIER18_Pos (18U)
6250#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
6251#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
6252#define EXTI_SWIER_SWIER19_Pos (19U)
6253#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)
6254#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk
6255#define EXTI_SWIER_SWIER20_Pos (20U)
6256#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos)
6257#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk
6258#define EXTI_SWIER_SWIER21_Pos (21U)
6259#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos)
6260#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk
6261#define EXTI_SWIER_SWIER22_Pos (22U)
6262#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos)
6263#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk
6264#define EXTI_SWIER_SWIER23_Pos (23U)
6265#define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos)
6266#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk
6268/******************* Bit definition for EXTI_PR register ********************/
6269#define EXTI_PR_PR0_Pos (0U)
6270#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
6271#define EXTI_PR_PR0 EXTI_PR_PR0_Msk
6272#define EXTI_PR_PR1_Pos (1U)
6273#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
6274#define EXTI_PR_PR1 EXTI_PR_PR1_Msk
6275#define EXTI_PR_PR2_Pos (2U)
6276#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
6277#define EXTI_PR_PR2 EXTI_PR_PR2_Msk
6278#define EXTI_PR_PR3_Pos (3U)
6279#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
6280#define EXTI_PR_PR3 EXTI_PR_PR3_Msk
6281#define EXTI_PR_PR4_Pos (4U)
6282#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
6283#define EXTI_PR_PR4 EXTI_PR_PR4_Msk
6284#define EXTI_PR_PR5_Pos (5U)
6285#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
6286#define EXTI_PR_PR5 EXTI_PR_PR5_Msk
6287#define EXTI_PR_PR6_Pos (6U)
6288#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
6289#define EXTI_PR_PR6 EXTI_PR_PR6_Msk
6290#define EXTI_PR_PR7_Pos (7U)
6291#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
6292#define EXTI_PR_PR7 EXTI_PR_PR7_Msk
6293#define EXTI_PR_PR8_Pos (8U)
6294#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
6295#define EXTI_PR_PR8 EXTI_PR_PR8_Msk
6296#define EXTI_PR_PR9_Pos (9U)
6297#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
6298#define EXTI_PR_PR9 EXTI_PR_PR9_Msk
6299#define EXTI_PR_PR10_Pos (10U)
6300#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
6301#define EXTI_PR_PR10 EXTI_PR_PR10_Msk
6302#define EXTI_PR_PR11_Pos (11U)
6303#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
6304#define EXTI_PR_PR11 EXTI_PR_PR11_Msk
6305#define EXTI_PR_PR12_Pos (12U)
6306#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
6307#define EXTI_PR_PR12 EXTI_PR_PR12_Msk
6308#define EXTI_PR_PR13_Pos (13U)
6309#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
6310#define EXTI_PR_PR13 EXTI_PR_PR13_Msk
6311#define EXTI_PR_PR14_Pos (14U)
6312#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
6313#define EXTI_PR_PR14 EXTI_PR_PR14_Msk
6314#define EXTI_PR_PR15_Pos (15U)
6315#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
6316#define EXTI_PR_PR15 EXTI_PR_PR15_Msk
6317#define EXTI_PR_PR16_Pos (16U)
6318#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
6319#define EXTI_PR_PR16 EXTI_PR_PR16_Msk
6320#define EXTI_PR_PR17_Pos (17U)
6321#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
6322#define EXTI_PR_PR17 EXTI_PR_PR17_Msk
6323#define EXTI_PR_PR18_Pos (18U)
6324#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
6325#define EXTI_PR_PR18 EXTI_PR_PR18_Msk
6326#define EXTI_PR_PR19_Pos (19U)
6327#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)
6328#define EXTI_PR_PR19 EXTI_PR_PR19_Msk
6329#define EXTI_PR_PR20_Pos (20U)
6330#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos)
6331#define EXTI_PR_PR20 EXTI_PR_PR20_Msk
6332#define EXTI_PR_PR21_Pos (21U)
6333#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos)
6334#define EXTI_PR_PR21 EXTI_PR_PR21_Msk
6335#define EXTI_PR_PR22_Pos (22U)
6336#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos)
6337#define EXTI_PR_PR22 EXTI_PR_PR22_Msk
6338#define EXTI_PR_PR23_Pos (23U)
6339#define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos)
6340#define EXTI_PR_PR23 EXTI_PR_PR23_Msk
6342/******************************************************************************/
6343/* */
6344/* FLASH */
6345/* */
6346/******************************************************************************/
6347/*
6348* @brief FLASH Total Sectors Number
6349*/
6350#define FLASH_SECTOR_TOTAL 8
6351
6352/******************* Bits definition for FLASH_ACR register *****************/
6353#define FLASH_ACR_LATENCY_Pos (0U)
6354#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
6355#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
6356#define FLASH_ACR_LATENCY_0WS 0x00000000U
6357#define FLASH_ACR_LATENCY_1WS 0x00000001U
6358#define FLASH_ACR_LATENCY_2WS 0x00000002U
6359#define FLASH_ACR_LATENCY_3WS 0x00000003U
6360#define FLASH_ACR_LATENCY_4WS 0x00000004U
6361#define FLASH_ACR_LATENCY_5WS 0x00000005U
6362#define FLASH_ACR_LATENCY_6WS 0x00000006U
6363#define FLASH_ACR_LATENCY_7WS 0x00000007U
6364#define FLASH_ACR_LATENCY_8WS 0x00000008U
6365#define FLASH_ACR_LATENCY_9WS 0x00000009U
6366#define FLASH_ACR_LATENCY_10WS 0x0000000AU
6367#define FLASH_ACR_LATENCY_11WS 0x0000000BU
6368#define FLASH_ACR_LATENCY_12WS 0x0000000CU
6369#define FLASH_ACR_LATENCY_13WS 0x0000000DU
6370#define FLASH_ACR_LATENCY_14WS 0x0000000EU
6371#define FLASH_ACR_LATENCY_15WS 0x0000000FU
6372#define FLASH_ACR_PRFTEN_Pos (8U)
6373#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos)
6374#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
6375#define FLASH_ACR_ARTEN_Pos (9U)
6376#define FLASH_ACR_ARTEN_Msk (0x1UL << FLASH_ACR_ARTEN_Pos)
6377#define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk
6378#define FLASH_ACR_ARTRST_Pos (11U)
6379#define FLASH_ACR_ARTRST_Msk (0x1UL << FLASH_ACR_ARTRST_Pos)
6380#define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk
6381
6382/******************* Bits definition for FLASH_SR register ******************/
6383#define FLASH_SR_EOP_Pos (0U)
6384#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
6385#define FLASH_SR_EOP FLASH_SR_EOP_Msk
6386#define FLASH_SR_OPERR_Pos (1U)
6387#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
6388#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
6389#define FLASH_SR_WRPERR_Pos (4U)
6390#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
6391#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
6392#define FLASH_SR_PGAERR_Pos (5U)
6393#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos)
6394#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
6395#define FLASH_SR_PGPERR_Pos (6U)
6396#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos)
6397#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
6398#define FLASH_SR_ERSERR_Pos (7U)
6399#define FLASH_SR_ERSERR_Msk (0x1UL << FLASH_SR_ERSERR_Pos)
6400#define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk
6401#define FLASH_SR_RDERR_Pos (8U)
6402#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos)
6403#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
6404#define FLASH_SR_BSY_Pos (16U)
6405#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
6406#define FLASH_SR_BSY FLASH_SR_BSY_Msk
6407
6408/******************* Bits definition for FLASH_CR register ******************/
6409#define FLASH_CR_PG_Pos (0U)
6410#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
6411#define FLASH_CR_PG FLASH_CR_PG_Msk
6412#define FLASH_CR_SER_Pos (1U)
6413#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
6414#define FLASH_CR_SER FLASH_CR_SER_Msk
6415#define FLASH_CR_MER_Pos (2U)
6416#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
6417#define FLASH_CR_MER FLASH_CR_MER_Msk
6418#define FLASH_CR_SNB_Pos (3U)
6419#define FLASH_CR_SNB_Msk (0xFUL << FLASH_CR_SNB_Pos)
6420#define FLASH_CR_SNB FLASH_CR_SNB_Msk
6421#define FLASH_CR_SNB_0 0x00000008U
6422#define FLASH_CR_SNB_1 0x00000010U
6423#define FLASH_CR_SNB_2 0x00000020U
6424#define FLASH_CR_SNB_3 0x00000040U
6425#define FLASH_CR_PSIZE_Pos (8U)
6426#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
6427#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
6428#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
6429#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
6430#define FLASH_CR_STRT_Pos (16U)
6431#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
6432#define FLASH_CR_STRT FLASH_CR_STRT_Msk
6433#define FLASH_CR_EOPIE_Pos (24U)
6434#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
6435#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
6436#define FLASH_CR_ERRIE_Pos (25U)
6437#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
6438#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
6439#define FLASH_CR_RDERRIE_Pos (26U)
6440#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos)
6441#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
6442#define FLASH_CR_LOCK_Pos (31U)
6443#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
6444#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
6445
6446/******************* Bits definition for FLASH_OPTCR register ***************/
6447#define FLASH_OPTCR_OPTLOCK_Pos (0U)
6448#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
6449#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
6450#define FLASH_OPTCR_OPTSTRT_Pos (1U)
6451#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)
6452#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
6453#define FLASH_OPTCR_BOR_LEV_Pos (2U)
6454#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)
6455#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
6456#define FLASH_OPTCR_BOR_LEV_0 (0x1UL << FLASH_OPTCR_BOR_LEV_Pos)
6457#define FLASH_OPTCR_BOR_LEV_1 (0x2UL << FLASH_OPTCR_BOR_LEV_Pos)
6458#define FLASH_OPTCR_WWDG_SW_Pos (4U)
6459#define FLASH_OPTCR_WWDG_SW_Msk (0x1UL << FLASH_OPTCR_WWDG_SW_Pos)
6460#define FLASH_OPTCR_WWDG_SW FLASH_OPTCR_WWDG_SW_Msk
6461#define FLASH_OPTCR_IWDG_SW_Pos (5U)
6462#define FLASH_OPTCR_IWDG_SW_Msk (0x1UL << FLASH_OPTCR_IWDG_SW_Pos)
6463#define FLASH_OPTCR_IWDG_SW FLASH_OPTCR_IWDG_SW_Msk
6464#define FLASH_OPTCR_nRST_STOP_Pos (6U)
6465#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)
6466#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
6467#define FLASH_OPTCR_nRST_STDBY_Pos (7U)
6468#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)
6469#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
6470#define FLASH_OPTCR_RDP_Pos (8U)
6471#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos)
6472#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
6473#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos)
6474#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos)
6475#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos)
6476#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos)
6477#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos)
6478#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos)
6479#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos)
6480#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos)
6481#define FLASH_OPTCR_nWRP_Pos (16U)
6482#define FLASH_OPTCR_nWRP_Msk (0xFFUL << FLASH_OPTCR_nWRP_Pos)
6483#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
6484#define FLASH_OPTCR_nWRP_0 0x00010000U
6485#define FLASH_OPTCR_nWRP_1 0x00020000U
6486#define FLASH_OPTCR_nWRP_2 0x00040000U
6487#define FLASH_OPTCR_nWRP_3 0x00080000U
6488#define FLASH_OPTCR_nWRP_4 0x00100000U
6489#define FLASH_OPTCR_nWRP_5 0x00200000U
6490#define FLASH_OPTCR_nWRP_6 0x00400000U
6491#define FLASH_OPTCR_nWRP_7 0x00800000U
6492#define FLASH_OPTCR_IWDG_STDBY_Pos (30U)
6493#define FLASH_OPTCR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTCR_IWDG_STDBY_Pos)
6494#define FLASH_OPTCR_IWDG_STDBY FLASH_OPTCR_IWDG_STDBY_Msk
6495#define FLASH_OPTCR_IWDG_STOP_Pos (31U)
6496#define FLASH_OPTCR_IWDG_STOP_Msk (0x1UL << FLASH_OPTCR_IWDG_STOP_Pos)
6497#define FLASH_OPTCR_IWDG_STOP FLASH_OPTCR_IWDG_STOP_Msk
6498
6499/******************* Bits definition for FLASH_OPTCR1 register ***************/
6500#define FLASH_OPTCR1_BOOT_ADD0_Pos (0U)
6501#define FLASH_OPTCR1_BOOT_ADD0_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD0_Pos)
6502#define FLASH_OPTCR1_BOOT_ADD0 FLASH_OPTCR1_BOOT_ADD0_Msk
6503#define FLASH_OPTCR1_BOOT_ADD1_Pos (16U)
6504#define FLASH_OPTCR1_BOOT_ADD1_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD1_Pos)
6505#define FLASH_OPTCR1_BOOT_ADD1 FLASH_OPTCR1_BOOT_ADD1_Msk
6506
6507/******************* Bits definition for FLASH_OPTCR2 register ***************/
6508#define FLASH_OPTCR2_PCROP_Pos (0U)
6509#define FLASH_OPTCR2_PCROP_Msk (0xFFUL << FLASH_OPTCR2_PCROP_Pos)
6510#define FLASH_OPTCR2_PCROP FLASH_OPTCR2_PCROP_Msk
6511#define FLASH_OPTCR2_PCROP_0 (0x01UL << FLASH_OPTCR2_PCROP_Pos)
6512#define FLASH_OPTCR2_PCROP_1 (0x02UL << FLASH_OPTCR2_PCROP_Pos)
6513#define FLASH_OPTCR2_PCROP_2 (0x04UL << FLASH_OPTCR2_PCROP_Pos)
6514#define FLASH_OPTCR2_PCROP_3 (0x08UL << FLASH_OPTCR2_PCROP_Pos)
6515#define FLASH_OPTCR2_PCROP_4 (0x10UL << FLASH_OPTCR2_PCROP_Pos)
6516#define FLASH_OPTCR2_PCROP_5 (0x20UL << FLASH_OPTCR2_PCROP_Pos)
6517#define FLASH_OPTCR2_PCROP_6 (0x40UL << FLASH_OPTCR2_PCROP_Pos)
6518#define FLASH_OPTCR2_PCROP_7 (0x80UL << FLASH_OPTCR2_PCROP_Pos)
6519#define FLASH_OPTCR2_PCROP_RDP_Pos (31U)
6520#define FLASH_OPTCR2_PCROP_RDP_Msk (0x1UL << FLASH_OPTCR2_PCROP_RDP_Pos)
6521#define FLASH_OPTCR2_PCROP_RDP FLASH_OPTCR2_PCROP_RDP_Msk
6522
6523/******************************************************************************/
6524/* */
6525/* Flexible Memory Controller */
6526/* */
6527/******************************************************************************/
6528/****************** Bit definition for FMC_BCR1 register *******************/
6529#define FMC_BCR1_MBKEN_Pos (0U)
6530#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos)
6531#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk
6532#define FMC_BCR1_MUXEN_Pos (1U)
6533#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos)
6534#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk
6535#define FMC_BCR1_MTYP_Pos (2U)
6536#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos)
6537#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk
6538#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos)
6539#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos)
6540#define FMC_BCR1_MWID_Pos (4U)
6541#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos)
6542#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk
6543#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos)
6544#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos)
6545#define FMC_BCR1_FACCEN_Pos (6U)
6546#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos)
6547#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk
6548#define FMC_BCR1_BURSTEN_Pos (8U)
6549#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos)
6550#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk
6551#define FMC_BCR1_WAITPOL_Pos (9U)
6552#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos)
6553#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk
6554#define FMC_BCR1_WRAPMOD_Pos (10U)
6555#define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos)
6556#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk
6557#define FMC_BCR1_WAITCFG_Pos (11U)
6558#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos)
6559#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk
6560#define FMC_BCR1_WREN_Pos (12U)
6561#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos)
6562#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk
6563#define FMC_BCR1_WAITEN_Pos (13U)
6564#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos)
6565#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk
6566#define FMC_BCR1_EXTMOD_Pos (14U)
6567#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos)
6568#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk
6569#define FMC_BCR1_ASYNCWAIT_Pos (15U)
6570#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos)
6571#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk
6572#define FMC_BCR1_CPSIZE_Pos (16U)
6573#define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos)
6574#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk
6575#define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos)
6576#define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos)
6577#define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos)
6578#define FMC_BCR1_CBURSTRW_Pos (19U)
6579#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos)
6580#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk
6581#define FMC_BCR1_CCLKEN_Pos (20U)
6582#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
6583#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
6584#define FMC_BCR1_WFDIS_Pos (21U)
6585#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
6586#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
6588/****************** Bit definition for FMC_BCR2 register *******************/
6589#define FMC_BCR2_MBKEN_Pos (0U)
6590#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos)
6591#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk
6592#define FMC_BCR2_MUXEN_Pos (1U)
6593#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos)
6594#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk
6595#define FMC_BCR2_MTYP_Pos (2U)
6596#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos)
6597#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk
6598#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos)
6599#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos)
6600#define FMC_BCR2_MWID_Pos (4U)
6601#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos)
6602#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk
6603#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos)
6604#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos)
6605#define FMC_BCR2_FACCEN_Pos (6U)
6606#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos)
6607#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk
6608#define FMC_BCR2_BURSTEN_Pos (8U)
6609#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos)
6610#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk
6611#define FMC_BCR2_WAITPOL_Pos (9U)
6612#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos)
6613#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk
6614#define FMC_BCR2_WRAPMOD_Pos (10U)
6615#define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos)
6616#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk
6617#define FMC_BCR2_WAITCFG_Pos (11U)
6618#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos)
6619#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk
6620#define FMC_BCR2_WREN_Pos (12U)
6621#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos)
6622#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk
6623#define FMC_BCR2_WAITEN_Pos (13U)
6624#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos)
6625#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk
6626#define FMC_BCR2_EXTMOD_Pos (14U)
6627#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos)
6628#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk
6629#define FMC_BCR2_ASYNCWAIT_Pos (15U)
6630#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos)
6631#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk
6632#define FMC_BCR2_CPSIZE_Pos (16U)
6633#define FMC_BCR2_CPSIZE_Msk (0x7UL << FMC_BCR2_CPSIZE_Pos)
6634#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk
6635#define FMC_BCR2_CPSIZE_0 (0x1UL << FMC_BCR2_CPSIZE_Pos)
6636#define FMC_BCR2_CPSIZE_1 (0x2UL << FMC_BCR2_CPSIZE_Pos)
6637#define FMC_BCR2_CPSIZE_2 (0x4UL << FMC_BCR2_CPSIZE_Pos)
6638#define FMC_BCR2_CBURSTRW_Pos (19U)
6639#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos)
6640#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk
6642/****************** Bit definition for FMC_BCR3 register *******************/
6643#define FMC_BCR3_MBKEN_Pos (0U)
6644#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos)
6645#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk
6646#define FMC_BCR3_MUXEN_Pos (1U)
6647#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos)
6648#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk
6649#define FMC_BCR3_MTYP_Pos (2U)
6650#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos)
6651#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk
6652#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos)
6653#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos)
6654#define FMC_BCR3_MWID_Pos (4U)
6655#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos)
6656#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk
6657#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos)
6658#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos)
6659#define FMC_BCR3_FACCEN_Pos (6U)
6660#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos)
6661#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk
6662#define FMC_BCR3_BURSTEN_Pos (8U)
6663#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos)
6664#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk
6665#define FMC_BCR3_WAITPOL_Pos (9U)
6666#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos)
6667#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk
6668#define FMC_BCR3_WRAPMOD_Pos (10U)
6669#define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos)
6670#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk
6671#define FMC_BCR3_WAITCFG_Pos (11U)
6672#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos)
6673#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk
6674#define FMC_BCR3_WREN_Pos (12U)
6675#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos)
6676#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk
6677#define FMC_BCR3_WAITEN_Pos (13U)
6678#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos)
6679#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk
6680#define FMC_BCR3_EXTMOD_Pos (14U)
6681#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos)
6682#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk
6683#define FMC_BCR3_ASYNCWAIT_Pos (15U)
6684#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos)
6685#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk
6686#define FMC_BCR3_CPSIZE_Pos (16U)
6687#define FMC_BCR3_CPSIZE_Msk (0x7UL << FMC_BCR3_CPSIZE_Pos)
6688#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk
6689#define FMC_BCR3_CPSIZE_0 (0x1UL << FMC_BCR3_CPSIZE_Pos)
6690#define FMC_BCR3_CPSIZE_1 (0x2UL << FMC_BCR3_CPSIZE_Pos)
6691#define FMC_BCR3_CPSIZE_2 (0x4UL << FMC_BCR3_CPSIZE_Pos)
6692#define FMC_BCR3_CBURSTRW_Pos (19U)
6693#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos)
6694#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk
6696/****************** Bit definition for FMC_BCR4 register *******************/
6697#define FMC_BCR4_MBKEN_Pos (0U)
6698#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos)
6699#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk
6700#define FMC_BCR4_MUXEN_Pos (1U)
6701#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos)
6702#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk
6703#define FMC_BCR4_MTYP_Pos (2U)
6704#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos)
6705#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk
6706#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos)
6707#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos)
6708#define FMC_BCR4_MWID_Pos (4U)
6709#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos)
6710#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk
6711#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos)
6712#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos)
6713#define FMC_BCR4_FACCEN_Pos (6U)
6714#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos)
6715#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk
6716#define FMC_BCR4_BURSTEN_Pos (8U)
6717#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos)
6718#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk
6719#define FMC_BCR4_WAITPOL_Pos (9U)
6720#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos)
6721#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk
6722#define FMC_BCR4_WRAPMOD_Pos (10U)
6723#define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos)
6724#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk
6725#define FMC_BCR4_WAITCFG_Pos (11U)
6726#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos)
6727#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk
6728#define FMC_BCR4_WREN_Pos (12U)
6729#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos)
6730#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk
6731#define FMC_BCR4_WAITEN_Pos (13U)
6732#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos)
6733#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk
6734#define FMC_BCR4_EXTMOD_Pos (14U)
6735#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos)
6736#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk
6737#define FMC_BCR4_ASYNCWAIT_Pos (15U)
6738#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos)
6739#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk
6740#define FMC_BCR4_CPSIZE_Pos (16U)
6741#define FMC_BCR4_CPSIZE_Msk (0x7UL << FMC_BCR4_CPSIZE_Pos)
6742#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk
6743#define FMC_BCR4_CPSIZE_0 (0x1UL << FMC_BCR4_CPSIZE_Pos)
6744#define FMC_BCR4_CPSIZE_1 (0x2UL << FMC_BCR4_CPSIZE_Pos)
6745#define FMC_BCR4_CPSIZE_2 (0x4UL << FMC_BCR4_CPSIZE_Pos)
6746#define FMC_BCR4_CBURSTRW_Pos (19U)
6747#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos)
6748#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk
6750/****************** Bit definition for FMC_BTR1 register ******************/
6751#define FMC_BTR1_ADDSET_Pos (0U)
6752#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos)
6753#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk
6754#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos)
6755#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos)
6756#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos)
6757#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos)
6758#define FMC_BTR1_ADDHLD_Pos (4U)
6759#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos)
6760#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk
6761#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos)
6762#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos)
6763#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos)
6764#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos)
6765#define FMC_BTR1_DATAST_Pos (8U)
6766#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos)
6767#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk
6768#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos)
6769#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos)
6770#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos)
6771#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos)
6772#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos)
6773#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos)
6774#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos)
6775#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos)
6776#define FMC_BTR1_BUSTURN_Pos (16U)
6777#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos)
6778#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk
6779#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos)
6780#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos)
6781#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos)
6782#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos)
6783#define FMC_BTR1_CLKDIV_Pos (20U)
6784#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos)
6785#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk
6786#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos)
6787#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos)
6788#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos)
6789#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos)
6790#define FMC_BTR1_DATLAT_Pos (24U)
6791#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos)
6792#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk
6793#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos)
6794#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos)
6795#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos)
6796#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos)
6797#define FMC_BTR1_ACCMOD_Pos (28U)
6798#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos)
6799#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk
6800#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos)
6801#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos)
6803/****************** Bit definition for FMC_BTR2 register *******************/
6804#define FMC_BTR2_ADDSET_Pos (0U)
6805#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos)
6806#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk
6807#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos)
6808#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos)
6809#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos)
6810#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos)
6811#define FMC_BTR2_ADDHLD_Pos (4U)
6812#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos)
6813#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk
6814#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos)
6815#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos)
6816#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos)
6817#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos)
6818#define FMC_BTR2_DATAST_Pos (8U)
6819#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos)
6820#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk
6821#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos)
6822#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos)
6823#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos)
6824#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos)
6825#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos)
6826#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos)
6827#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos)
6828#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos)
6829#define FMC_BTR2_BUSTURN_Pos (16U)
6830#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos)
6831#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk
6832#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos)
6833#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos)
6834#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos)
6835#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos)
6836#define FMC_BTR2_CLKDIV_Pos (20U)
6837#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos)
6838#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk
6839#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos)
6840#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos)
6841#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos)
6842#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos)
6843#define FMC_BTR2_DATLAT_Pos (24U)
6844#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos)
6845#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk
6846#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos)
6847#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos)
6848#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos)
6849#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos)
6850#define FMC_BTR2_ACCMOD_Pos (28U)
6851#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos)
6852#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk
6853#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos)
6854#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos)
6856/******************* Bit definition for FMC_BTR3 register *******************/
6857#define FMC_BTR3_ADDSET_Pos (0U)
6858#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos)
6859#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk
6860#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos)
6861#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos)
6862#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos)
6863#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos)
6864#define FMC_BTR3_ADDHLD_Pos (4U)
6865#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos)
6866#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk
6867#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos)
6868#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos)
6869#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos)
6870#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos)
6871#define FMC_BTR3_DATAST_Pos (8U)
6872#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos)
6873#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk
6874#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos)
6875#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos)
6876#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos)
6877#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos)
6878#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos)
6879#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos)
6880#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos)
6881#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos)
6882#define FMC_BTR3_BUSTURN_Pos (16U)
6883#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos)
6884#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk
6885#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos)
6886#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos)
6887#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos)
6888#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos)
6889#define FMC_BTR3_CLKDIV_Pos (20U)
6890#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos)
6891#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk
6892#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos)
6893#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos)
6894#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos)
6895#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos)
6896#define FMC_BTR3_DATLAT_Pos (24U)
6897#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos)
6898#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk
6899#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos)
6900#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos)
6901#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos)
6902#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos)
6903#define FMC_BTR3_ACCMOD_Pos (28U)
6904#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos)
6905#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk
6906#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos)
6907#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos)
6909/****************** Bit definition for FMC_BTR4 register *******************/
6910#define FMC_BTR4_ADDSET_Pos (0U)
6911#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos)
6912#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk
6913#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos)
6914#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos)
6915#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos)
6916#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos)
6917#define FMC_BTR4_ADDHLD_Pos (4U)
6918#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos)
6919#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk
6920#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos)
6921#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos)
6922#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos)
6923#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos)
6924#define FMC_BTR4_DATAST_Pos (8U)
6925#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos)
6926#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk
6927#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos)
6928#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos)
6929#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos)
6930#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos)
6931#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos)
6932#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos)
6933#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos)
6934#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos)
6935#define FMC_BTR4_BUSTURN_Pos (16U)
6936#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos)
6937#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk
6938#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos)
6939#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos)
6940#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos)
6941#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos)
6942#define FMC_BTR4_CLKDIV_Pos (20U)
6943#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos)
6944#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk
6945#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos)
6946#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos)
6947#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos)
6948#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos)
6949#define FMC_BTR4_DATLAT_Pos (24U)
6950#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos)
6951#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk
6952#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos)
6953#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos)
6954#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos)
6955#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos)
6956#define FMC_BTR4_ACCMOD_Pos (28U)
6957#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos)
6958#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk
6959#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos)
6960#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos)
6962/****************** Bit definition for FMC_BWTR1 register ******************/
6963#define FMC_BWTR1_ADDSET_Pos (0U)
6964#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos)
6965#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk
6966#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos)
6967#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos)
6968#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos)
6969#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos)
6970#define FMC_BWTR1_ADDHLD_Pos (4U)
6971#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos)
6972#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk
6973#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos)
6974#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos)
6975#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos)
6976#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos)
6977#define FMC_BWTR1_DATAST_Pos (8U)
6978#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos)
6979#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk
6980#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos)
6981#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos)
6982#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos)
6983#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos)
6984#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos)
6985#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos)
6986#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos)
6987#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos)
6988#define FMC_BWTR1_BUSTURN_Pos (16U)
6989#define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos)
6990#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk
6991#define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos)
6992#define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos)
6993#define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos)
6994#define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos)
6995#define FMC_BWTR1_ACCMOD_Pos (28U)
6996#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos)
6997#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk
6998#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos)
6999#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos)
7001/****************** Bit definition for FMC_BWTR2 register ******************/
7002#define FMC_BWTR2_ADDSET_Pos (0U)
7003#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos)
7004#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk
7005#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos)
7006#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos)
7007#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos)
7008#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos)
7009#define FMC_BWTR2_ADDHLD_Pos (4U)
7010#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos)
7011#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk
7012#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos)
7013#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos)
7014#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos)
7015#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos)
7016#define FMC_BWTR2_DATAST_Pos (8U)
7017#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos)
7018#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk
7019#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos)
7020#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos)
7021#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos)
7022#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos)
7023#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos)
7024#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos)
7025#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos)
7026#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos)
7027#define FMC_BWTR2_BUSTURN_Pos (16U)
7028#define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos)
7029#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk
7030#define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos)
7031#define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos)
7032#define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos)
7033#define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos)
7034#define FMC_BWTR2_ACCMOD_Pos (28U)
7035#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos)
7036#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk
7037#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos)
7038#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos)
7040/****************** Bit definition for FMC_BWTR3 register ******************/
7041#define FMC_BWTR3_ADDSET_Pos (0U)
7042#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos)
7043#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk
7044#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos)
7045#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos)
7046#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos)
7047#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos)
7048#define FMC_BWTR3_ADDHLD_Pos (4U)
7049#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos)
7050#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk
7051#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos)
7052#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos)
7053#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos)
7054#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos)
7055#define FMC_BWTR3_DATAST_Pos (8U)
7056#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos)
7057#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk
7058#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos)
7059#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos)
7060#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos)
7061#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos)
7062#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos)
7063#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos)
7064#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos)
7065#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos)
7066#define FMC_BWTR3_BUSTURN_Pos (16U)
7067#define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos)
7068#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk
7069#define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos)
7070#define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos)
7071#define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos)
7072#define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos)
7073#define FMC_BWTR3_ACCMOD_Pos (28U)
7074#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos)
7075#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk
7076#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos)
7077#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos)
7079/****************** Bit definition for FMC_BWTR4 register ******************/
7080#define FMC_BWTR4_ADDSET_Pos (0U)
7081#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos)
7082#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk
7083#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos)
7084#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos)
7085#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos)
7086#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos)
7087#define FMC_BWTR4_ADDHLD_Pos (4U)
7088#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos)
7089#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk
7090#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos)
7091#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos)
7092#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos)
7093#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos)
7094#define FMC_BWTR4_DATAST_Pos (8U)
7095#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos)
7096#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk
7097#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos)
7098#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos)
7099#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos)
7100#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos)
7101#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos)
7102#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos)
7103#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos)
7104#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos)
7105#define FMC_BWTR4_BUSTURN_Pos (16U)
7106#define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos)
7107#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk
7108#define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos)
7109#define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos)
7110#define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos)
7111#define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos)
7112#define FMC_BWTR4_ACCMOD_Pos (28U)
7113#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos)
7114#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk
7115#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos)
7116#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos)
7118/****************** Bit definition for FMC_PCR register *******************/
7119#define FMC_PCR_PWAITEN_Pos (1U)
7120#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
7121#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
7122#define FMC_PCR_PBKEN_Pos (2U)
7123#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
7124#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
7125#define FMC_PCR_PTYP_Pos (3U)
7126#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos)
7127#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk
7128#define FMC_PCR_PWID_Pos (4U)
7129#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
7130#define FMC_PCR_PWID FMC_PCR_PWID_Msk
7131#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
7132#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
7133#define FMC_PCR_ECCEN_Pos (6U)
7134#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
7135#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
7136#define FMC_PCR_TCLR_Pos (9U)
7137#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
7138#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
7139#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
7140#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
7141#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
7142#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
7143#define FMC_PCR_TAR_Pos (13U)
7144#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
7145#define FMC_PCR_TAR FMC_PCR_TAR_Msk
7146#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
7147#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
7148#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
7149#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
7150#define FMC_PCR_ECCPS_Pos (17U)
7151#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
7152#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
7153#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
7154#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
7155#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
7157/******************* Bit definition for FMC_SR register *******************/
7158#define FMC_SR_IRS_Pos (0U)
7159#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
7160#define FMC_SR_IRS FMC_SR_IRS_Msk
7161#define FMC_SR_ILS_Pos (1U)
7162#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
7163#define FMC_SR_ILS FMC_SR_ILS_Msk
7164#define FMC_SR_IFS_Pos (2U)
7165#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
7166#define FMC_SR_IFS FMC_SR_IFS_Msk
7167#define FMC_SR_IREN_Pos (3U)
7168#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
7169#define FMC_SR_IREN FMC_SR_IREN_Msk
7170#define FMC_SR_ILEN_Pos (4U)
7171#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
7172#define FMC_SR_ILEN FMC_SR_ILEN_Msk
7173#define FMC_SR_IFEN_Pos (5U)
7174#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
7175#define FMC_SR_IFEN FMC_SR_IFEN_Msk
7176#define FMC_SR_FEMPT_Pos (6U)
7177#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
7178#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
7180/****************** Bit definition for FMC_PMEM register ******************/
7181#define FMC_PMEM_MEMSET3_Pos (0U)
7182#define FMC_PMEM_MEMSET3_Msk (0xFFUL << FMC_PMEM_MEMSET3_Pos)
7183#define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk
7184#define FMC_PMEM_MEMSET3_0 (0x01UL << FMC_PMEM_MEMSET3_Pos)
7185#define FMC_PMEM_MEMSET3_1 (0x02UL << FMC_PMEM_MEMSET3_Pos)
7186#define FMC_PMEM_MEMSET3_2 (0x04UL << FMC_PMEM_MEMSET3_Pos)
7187#define FMC_PMEM_MEMSET3_3 (0x08UL << FMC_PMEM_MEMSET3_Pos)
7188#define FMC_PMEM_MEMSET3_4 (0x10UL << FMC_PMEM_MEMSET3_Pos)
7189#define FMC_PMEM_MEMSET3_5 (0x20UL << FMC_PMEM_MEMSET3_Pos)
7190#define FMC_PMEM_MEMSET3_6 (0x40UL << FMC_PMEM_MEMSET3_Pos)
7191#define FMC_PMEM_MEMSET3_7 (0x80UL << FMC_PMEM_MEMSET3_Pos)
7192#define FMC_PMEM_MEMWAIT3_Pos (8U)
7193#define FMC_PMEM_MEMWAIT3_Msk (0xFFUL << FMC_PMEM_MEMWAIT3_Pos)
7194#define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk
7195#define FMC_PMEM_MEMWAIT3_0 (0x01UL << FMC_PMEM_MEMWAIT3_Pos)
7196#define FMC_PMEM_MEMWAIT3_1 (0x02UL << FMC_PMEM_MEMWAIT3_Pos)
7197#define FMC_PMEM_MEMWAIT3_2 (0x04UL << FMC_PMEM_MEMWAIT3_Pos)
7198#define FMC_PMEM_MEMWAIT3_3 (0x08UL << FMC_PMEM_MEMWAIT3_Pos)
7199#define FMC_PMEM_MEMWAIT3_4 (0x10UL << FMC_PMEM_MEMWAIT3_Pos)
7200#define FMC_PMEM_MEMWAIT3_5 (0x20UL << FMC_PMEM_MEMWAIT3_Pos)
7201#define FMC_PMEM_MEMWAIT3_6 (0x40UL << FMC_PMEM_MEMWAIT3_Pos)
7202#define FMC_PMEM_MEMWAIT3_7 (0x80UL << FMC_PMEM_MEMWAIT3_Pos)
7203#define FMC_PMEM_MEMHOLD3_Pos (16U)
7204#define FMC_PMEM_MEMHOLD3_Msk (0xFFUL << FMC_PMEM_MEMHOLD3_Pos)
7205#define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk
7206#define FMC_PMEM_MEMHOLD3_0 (0x01UL << FMC_PMEM_MEMHOLD3_Pos)
7207#define FMC_PMEM_MEMHOLD3_1 (0x02UL << FMC_PMEM_MEMHOLD3_Pos)
7208#define FMC_PMEM_MEMHOLD3_2 (0x04UL << FMC_PMEM_MEMHOLD3_Pos)
7209#define FMC_PMEM_MEMHOLD3_3 (0x08UL << FMC_PMEM_MEMHOLD3_Pos)
7210#define FMC_PMEM_MEMHOLD3_4 (0x10UL << FMC_PMEM_MEMHOLD3_Pos)
7211#define FMC_PMEM_MEMHOLD3_5 (0x20UL << FMC_PMEM_MEMHOLD3_Pos)
7212#define FMC_PMEM_MEMHOLD3_6 (0x40UL << FMC_PMEM_MEMHOLD3_Pos)
7213#define FMC_PMEM_MEMHOLD3_7 (0x80UL << FMC_PMEM_MEMHOLD3_Pos)
7214#define FMC_PMEM_MEMHIZ3_Pos (24U)
7215#define FMC_PMEM_MEMHIZ3_Msk (0xFFUL << FMC_PMEM_MEMHIZ3_Pos)
7216#define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk
7217#define FMC_PMEM_MEMHIZ3_0 (0x01UL << FMC_PMEM_MEMHIZ3_Pos)
7218#define FMC_PMEM_MEMHIZ3_1 (0x02UL << FMC_PMEM_MEMHIZ3_Pos)
7219#define FMC_PMEM_MEMHIZ3_2 (0x04UL << FMC_PMEM_MEMHIZ3_Pos)
7220#define FMC_PMEM_MEMHIZ3_3 (0x08UL << FMC_PMEM_MEMHIZ3_Pos)
7221#define FMC_PMEM_MEMHIZ3_4 (0x10UL << FMC_PMEM_MEMHIZ3_Pos)
7222#define FMC_PMEM_MEMHIZ3_5 (0x20UL << FMC_PMEM_MEMHIZ3_Pos)
7223#define FMC_PMEM_MEMHIZ3_6 (0x40UL << FMC_PMEM_MEMHIZ3_Pos)
7224#define FMC_PMEM_MEMHIZ3_7 (0x80UL << FMC_PMEM_MEMHIZ3_Pos)
7226/****************** Bit definition for FMC_PATT register ******************/
7227#define FMC_PATT_ATTSET3_Pos (0U)
7228#define FMC_PATT_ATTSET3_Msk (0xFFUL << FMC_PATT_ATTSET3_Pos)
7229#define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk
7230#define FMC_PATT_ATTSET3_0 (0x01UL << FMC_PATT_ATTSET3_Pos)
7231#define FMC_PATT_ATTSET3_1 (0x02UL << FMC_PATT_ATTSET3_Pos)
7232#define FMC_PATT_ATTSET3_2 (0x04UL << FMC_PATT_ATTSET3_Pos)
7233#define FMC_PATT_ATTSET3_3 (0x08UL << FMC_PATT_ATTSET3_Pos)
7234#define FMC_PATT_ATTSET3_4 (0x10UL << FMC_PATT_ATTSET3_Pos)
7235#define FMC_PATT_ATTSET3_5 (0x20UL << FMC_PATT_ATTSET3_Pos)
7236#define FMC_PATT_ATTSET3_6 (0x40UL << FMC_PATT_ATTSET3_Pos)
7237#define FMC_PATT_ATTSET3_7 (0x80UL << FMC_PATT_ATTSET3_Pos)
7238#define FMC_PATT_ATTWAIT3_Pos (8U)
7239#define FMC_PATT_ATTWAIT3_Msk (0xFFUL << FMC_PATT_ATTWAIT3_Pos)
7240#define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk
7241#define FMC_PATT_ATTWAIT3_0 (0x01UL << FMC_PATT_ATTWAIT3_Pos)
7242#define FMC_PATT_ATTWAIT3_1 (0x02UL << FMC_PATT_ATTWAIT3_Pos)
7243#define FMC_PATT_ATTWAIT3_2 (0x04UL << FMC_PATT_ATTWAIT3_Pos)
7244#define FMC_PATT_ATTWAIT3_3 (0x08UL << FMC_PATT_ATTWAIT3_Pos)
7245#define FMC_PATT_ATTWAIT3_4 (0x10UL << FMC_PATT_ATTWAIT3_Pos)
7246#define FMC_PATT_ATTWAIT3_5 (0x20UL << FMC_PATT_ATTWAIT3_Pos)
7247#define FMC_PATT_ATTWAIT3_6 (0x40UL << FMC_PATT_ATTWAIT3_Pos)
7248#define FMC_PATT_ATTWAIT3_7 (0x80UL << FMC_PATT_ATTWAIT3_Pos)
7249#define FMC_PATT_ATTHOLD3_Pos (16U)
7250#define FMC_PATT_ATTHOLD3_Msk (0xFFUL << FMC_PATT_ATTHOLD3_Pos)
7251#define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk
7252#define FMC_PATT_ATTHOLD3_0 (0x01UL << FMC_PATT_ATTHOLD3_Pos)
7253#define FMC_PATT_ATTHOLD3_1 (0x02UL << FMC_PATT_ATTHOLD3_Pos)
7254#define FMC_PATT_ATTHOLD3_2 (0x04UL << FMC_PATT_ATTHOLD3_Pos)
7255#define FMC_PATT_ATTHOLD3_3 (0x08UL << FMC_PATT_ATTHOLD3_Pos)
7256#define FMC_PATT_ATTHOLD3_4 (0x10UL << FMC_PATT_ATTHOLD3_Pos)
7257#define FMC_PATT_ATTHOLD3_5 (0x20UL << FMC_PATT_ATTHOLD3_Pos)
7258#define FMC_PATT_ATTHOLD3_6 (0x40UL << FMC_PATT_ATTHOLD3_Pos)
7259#define FMC_PATT_ATTHOLD3_7 (0x80UL << FMC_PATT_ATTHOLD3_Pos)
7260#define FMC_PATT_ATTHIZ3_Pos (24U)
7261#define FMC_PATT_ATTHIZ3_Msk (0xFFUL << FMC_PATT_ATTHIZ3_Pos)
7262#define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk
7263#define FMC_PATT_ATTHIZ3_0 (0x01UL << FMC_PATT_ATTHIZ3_Pos)
7264#define FMC_PATT_ATTHIZ3_1 (0x02UL << FMC_PATT_ATTHIZ3_Pos)
7265#define FMC_PATT_ATTHIZ3_2 (0x04UL << FMC_PATT_ATTHIZ3_Pos)
7266#define FMC_PATT_ATTHIZ3_3 (0x08UL << FMC_PATT_ATTHIZ3_Pos)
7267#define FMC_PATT_ATTHIZ3_4 (0x10UL << FMC_PATT_ATTHIZ3_Pos)
7268#define FMC_PATT_ATTHIZ3_5 (0x20UL << FMC_PATT_ATTHIZ3_Pos)
7269#define FMC_PATT_ATTHIZ3_6 (0x40UL << FMC_PATT_ATTHIZ3_Pos)
7270#define FMC_PATT_ATTHIZ3_7 (0x80UL << FMC_PATT_ATTHIZ3_Pos)
7272/****************** Bit definition for FMC_ECCR register ******************/
7273#define FMC_ECCR_ECC3_Pos (0U)
7274#define FMC_ECCR_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC3_Pos)
7275#define FMC_ECCR_ECC3 FMC_ECCR_ECC3_Msk
7277/****************** Bit definition for FMC_SDCR1 register ******************/
7278#define FMC_SDCR1_NC_Pos (0U)
7279#define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos)
7280#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk
7281#define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos)
7282#define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos)
7283#define FMC_SDCR1_NR_Pos (2U)
7284#define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos)
7285#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk
7286#define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos)
7287#define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos)
7288#define FMC_SDCR1_MWID_Pos (4U)
7289#define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos)
7290#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk
7291#define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos)
7292#define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos)
7293#define FMC_SDCR1_NB_Pos (6U)
7294#define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos)
7295#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk
7296#define FMC_SDCR1_CAS_Pos (7U)
7297#define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos)
7298#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk
7299#define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos)
7300#define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos)
7301#define FMC_SDCR1_WP_Pos (9U)
7302#define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos)
7303#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk
7304#define FMC_SDCR1_SDCLK_Pos (10U)
7305#define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos)
7306#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk
7307#define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos)
7308#define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos)
7309#define FMC_SDCR1_RBURST_Pos (12U)
7310#define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos)
7311#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk
7312#define FMC_SDCR1_RPIPE_Pos (13U)
7313#define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos)
7314#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk
7315#define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos)
7316#define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos)
7318/****************** Bit definition for FMC_SDCR2 register ******************/
7319#define FMC_SDCR2_NC_Pos (0U)
7320#define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos)
7321#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk
7322#define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos)
7323#define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos)
7324#define FMC_SDCR2_NR_Pos (2U)
7325#define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos)
7326#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk
7327#define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos)
7328#define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos)
7329#define FMC_SDCR2_MWID_Pos (4U)
7330#define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos)
7331#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk
7332#define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos)
7333#define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos)
7334#define FMC_SDCR2_NB_Pos (6U)
7335#define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos)
7336#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk
7337#define FMC_SDCR2_CAS_Pos (7U)
7338#define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos)
7339#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk
7340#define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos)
7341#define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos)
7342#define FMC_SDCR2_WP_Pos (9U)
7343#define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos)
7344#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk
7345#define FMC_SDCR2_SDCLK_Pos (10U)
7346#define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos)
7347#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk
7348#define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos)
7349#define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos)
7350#define FMC_SDCR2_RBURST_Pos (12U)
7351#define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos)
7352#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk
7353#define FMC_SDCR2_RPIPE_Pos (13U)
7354#define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos)
7355#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk
7356#define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos)
7357#define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos)
7359/****************** Bit definition for FMC_SDTR1 register ******************/
7360#define FMC_SDTR1_TMRD_Pos (0U)
7361#define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos)
7362#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk
7363#define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos)
7364#define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos)
7365#define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos)
7366#define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos)
7367#define FMC_SDTR1_TXSR_Pos (4U)
7368#define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos)
7369#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk
7370#define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos)
7371#define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos)
7372#define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos)
7373#define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos)
7374#define FMC_SDTR1_TRAS_Pos (8U)
7375#define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos)
7376#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk
7377#define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos)
7378#define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos)
7379#define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos)
7380#define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos)
7381#define FMC_SDTR1_TRC_Pos (12U)
7382#define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos)
7383#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk
7384#define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos)
7385#define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos)
7386#define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos)
7387#define FMC_SDTR1_TWR_Pos (16U)
7388#define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos)
7389#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk
7390#define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos)
7391#define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos)
7392#define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos)
7393#define FMC_SDTR1_TRP_Pos (20U)
7394#define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos)
7395#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk
7396#define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos)
7397#define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos)
7398#define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos)
7399#define FMC_SDTR1_TRCD_Pos (24U)
7400#define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos)
7401#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk
7402#define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos)
7403#define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos)
7404#define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos)
7406/****************** Bit definition for FMC_SDTR2 register ******************/
7407#define FMC_SDTR2_TMRD_Pos (0U)
7408#define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos)
7409#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk
7410#define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos)
7411#define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos)
7412#define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos)
7413#define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos)
7414#define FMC_SDTR2_TXSR_Pos (4U)
7415#define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos)
7416#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk
7417#define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos)
7418#define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos)
7419#define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos)
7420#define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos)
7421#define FMC_SDTR2_TRAS_Pos (8U)
7422#define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos)
7423#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk
7424#define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos)
7425#define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos)
7426#define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos)
7427#define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos)
7428#define FMC_SDTR2_TRC_Pos (12U)
7429#define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos)
7430#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk
7431#define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos)
7432#define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos)
7433#define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos)
7434#define FMC_SDTR2_TWR_Pos (16U)
7435#define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos)
7436#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk
7437#define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos)
7438#define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos)
7439#define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos)
7440#define FMC_SDTR2_TRP_Pos (20U)
7441#define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos)
7442#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk
7443#define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos)
7444#define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos)
7445#define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos)
7446#define FMC_SDTR2_TRCD_Pos (24U)
7447#define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos)
7448#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk
7449#define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos)
7450#define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos)
7451#define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos)
7453/****************** Bit definition for FMC_SDCMR register ******************/
7454#define FMC_SDCMR_MODE_Pos (0U)
7455#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
7456#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
7457#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
7458#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
7459#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos)
7460#define FMC_SDCMR_CTB2_Pos (3U)
7461#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
7462#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
7463#define FMC_SDCMR_CTB1_Pos (4U)
7464#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
7465#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
7466#define FMC_SDCMR_NRFS_Pos (5U)
7467#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
7468#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
7469#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
7470#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
7471#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
7472#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
7473#define FMC_SDCMR_MRD_Pos (9U)
7474#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
7475#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
7477/****************** Bit definition for FMC_SDRTR register ******************/
7478#define FMC_SDRTR_CRE_Pos (0U)
7479#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
7480#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
7481#define FMC_SDRTR_COUNT_Pos (1U)
7482#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
7483#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
7484#define FMC_SDRTR_REIE_Pos (14U)
7485#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
7486#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
7488/****************** Bit definition for FMC_SDSR register ******************/
7489#define FMC_SDSR_RE_Pos (0U)
7490#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
7491#define FMC_SDSR_RE FMC_SDSR_RE_Msk
7492#define FMC_SDSR_MODES1_Pos (1U)
7493#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
7494#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
7495#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
7496#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
7497#define FMC_SDSR_MODES2_Pos (3U)
7498#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
7499#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
7500#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
7501#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
7502#define FMC_SDSR_BUSY_Pos (5U)
7503#define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos)
7504#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk
7506/******************************************************************************/
7507/* */
7508/* General Purpose I/O */
7509/* */
7510/******************************************************************************/
7511/****************** Bits definition for GPIO_MODER register *****************/
7512#define GPIO_MODER_MODER0_Pos (0U)
7513#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos)
7514#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
7515#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos)
7516#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos)
7517#define GPIO_MODER_MODER1_Pos (2U)
7518#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos)
7519#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
7520#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos)
7521#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos)
7522#define GPIO_MODER_MODER2_Pos (4U)
7523#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos)
7524#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
7525#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos)
7526#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos)
7527#define GPIO_MODER_MODER3_Pos (6U)
7528#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos)
7529#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
7530#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos)
7531#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos)
7532#define GPIO_MODER_MODER4_Pos (8U)
7533#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos)
7534#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
7535#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos)
7536#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos)
7537#define GPIO_MODER_MODER5_Pos (10U)
7538#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos)
7539#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
7540#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos)
7541#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos)
7542#define GPIO_MODER_MODER6_Pos (12U)
7543#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos)
7544#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
7545#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos)
7546#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos)
7547#define GPIO_MODER_MODER7_Pos (14U)
7548#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos)
7549#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
7550#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos)
7551#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos)
7552#define GPIO_MODER_MODER8_Pos (16U)
7553#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos)
7554#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
7555#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos)
7556#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos)
7557#define GPIO_MODER_MODER9_Pos (18U)
7558#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos)
7559#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
7560#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos)
7561#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos)
7562#define GPIO_MODER_MODER10_Pos (20U)
7563#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos)
7564#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
7565#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos)
7566#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos)
7567#define GPIO_MODER_MODER11_Pos (22U)
7568#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos)
7569#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
7570#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos)
7571#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos)
7572#define GPIO_MODER_MODER12_Pos (24U)
7573#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos)
7574#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
7575#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos)
7576#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos)
7577#define GPIO_MODER_MODER13_Pos (26U)
7578#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos)
7579#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
7580#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos)
7581#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos)
7582#define GPIO_MODER_MODER14_Pos (28U)
7583#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos)
7584#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
7585#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos)
7586#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos)
7587#define GPIO_MODER_MODER15_Pos (30U)
7588#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos)
7589#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
7590#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos)
7591#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos)
7593/****************** Bits definition for GPIO_OTYPER register ****************/
7594#define GPIO_OTYPER_OT0_Pos (0U)
7595#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
7596#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
7597#define GPIO_OTYPER_OT1_Pos (1U)
7598#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
7599#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
7600#define GPIO_OTYPER_OT2_Pos (2U)
7601#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
7602#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
7603#define GPIO_OTYPER_OT3_Pos (3U)
7604#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
7605#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
7606#define GPIO_OTYPER_OT4_Pos (4U)
7607#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
7608#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
7609#define GPIO_OTYPER_OT5_Pos (5U)
7610#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
7611#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
7612#define GPIO_OTYPER_OT6_Pos (6U)
7613#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
7614#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
7615#define GPIO_OTYPER_OT7_Pos (7U)
7616#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
7617#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
7618#define GPIO_OTYPER_OT8_Pos (8U)
7619#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
7620#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
7621#define GPIO_OTYPER_OT9_Pos (9U)
7622#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
7623#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
7624#define GPIO_OTYPER_OT10_Pos (10U)
7625#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
7626#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
7627#define GPIO_OTYPER_OT11_Pos (11U)
7628#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
7629#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
7630#define GPIO_OTYPER_OT12_Pos (12U)
7631#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
7632#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
7633#define GPIO_OTYPER_OT13_Pos (13U)
7634#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
7635#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
7636#define GPIO_OTYPER_OT14_Pos (14U)
7637#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
7638#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
7639#define GPIO_OTYPER_OT15_Pos (15U)
7640#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
7641#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
7642
7643/* Legacy defines */
7644#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
7645#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
7646#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
7647#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
7648#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
7649#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
7650#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
7651#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
7652#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
7653#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
7654#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
7655#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
7656#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
7657#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
7658#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
7659#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
7660
7661/****************** Bits definition for GPIO_OSPEEDR register ***************/
7662#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
7663#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
7664#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
7665#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
7666#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos)
7667#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
7668#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
7669#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
7670#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
7671#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos)
7672#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
7673#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
7674#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
7675#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
7676#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos)
7677#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
7678#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
7679#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
7680#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
7681#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos)
7682#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
7683#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
7684#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
7685#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
7686#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos)
7687#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
7688#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
7689#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
7690#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
7691#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos)
7692#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
7693#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
7694#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
7695#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
7696#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos)
7697#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
7698#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
7699#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
7700#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
7701#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos)
7702#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
7703#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
7704#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
7705#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
7706#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos)
7707#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
7708#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
7709#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
7710#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
7711#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos)
7712#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
7713#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
7714#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
7715#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
7716#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos)
7717#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
7718#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
7719#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
7720#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
7721#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos)
7722#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
7723#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
7724#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
7725#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
7726#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos)
7727#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
7728#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
7729#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
7730#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
7731#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos)
7732#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
7733#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
7734#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
7735#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
7736#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos)
7737#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
7738#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
7739#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
7740#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
7741#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos)
7743/* legacy defines */
7744#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos
7745#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk
7746#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
7747#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
7748#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
7749#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos
7750#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk
7751#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
7752#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
7753#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
7754#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos
7755#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk
7756#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
7757#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
7758#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
7759#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos
7760#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk
7761#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
7762#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
7763#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
7764#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos
7765#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk
7766#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
7767#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
7768#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
7769#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos
7770#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk
7771#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
7772#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
7773#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
7774#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos
7775#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk
7776#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
7777#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
7778#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
7779#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos
7780#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk
7781#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
7782#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
7783#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
7784#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos
7785#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk
7786#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
7787#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
7788#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
7789#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos
7790#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk
7791#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
7792#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
7793#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
7794#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos
7795#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk
7796#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
7797#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
7798#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
7799#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos
7800#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk
7801#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
7802#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
7803#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
7804#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos
7805#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk
7806#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
7807#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
7808#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
7809#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos
7810#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk
7811#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
7812#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
7813#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
7814#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos
7815#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk
7816#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
7817#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
7818#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
7819#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos
7820#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk
7821#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
7822#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
7823#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
7824
7825/****************** Bits definition for GPIO_PUPDR register *****************/
7826#define GPIO_PUPDR_PUPDR0_Pos (0U)
7827#define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos)
7828#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
7829#define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos)
7830#define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos)
7831#define GPIO_PUPDR_PUPDR1_Pos (2U)
7832#define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos)
7833#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
7834#define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos)
7835#define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos)
7836#define GPIO_PUPDR_PUPDR2_Pos (4U)
7837#define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos)
7838#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
7839#define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos)
7840#define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos)
7841#define GPIO_PUPDR_PUPDR3_Pos (6U)
7842#define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos)
7843#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
7844#define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos)
7845#define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos)
7846#define GPIO_PUPDR_PUPDR4_Pos (8U)
7847#define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos)
7848#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
7849#define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos)
7850#define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos)
7851#define GPIO_PUPDR_PUPDR5_Pos (10U)
7852#define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos)
7853#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
7854#define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos)
7855#define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos)
7856#define GPIO_PUPDR_PUPDR6_Pos (12U)
7857#define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos)
7858#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
7859#define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos)
7860#define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos)
7861#define GPIO_PUPDR_PUPDR7_Pos (14U)
7862#define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos)
7863#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
7864#define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos)
7865#define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos)
7866#define GPIO_PUPDR_PUPDR8_Pos (16U)
7867#define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos)
7868#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
7869#define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos)
7870#define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos)
7871#define GPIO_PUPDR_PUPDR9_Pos (18U)
7872#define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos)
7873#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
7874#define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos)
7875#define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos)
7876#define GPIO_PUPDR_PUPDR10_Pos (20U)
7877#define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos)
7878#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
7879#define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos)
7880#define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos)
7881#define GPIO_PUPDR_PUPDR11_Pos (22U)
7882#define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos)
7883#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
7884#define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos)
7885#define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos)
7886#define GPIO_PUPDR_PUPDR12_Pos (24U)
7887#define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos)
7888#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
7889#define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos)
7890#define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos)
7891#define GPIO_PUPDR_PUPDR13_Pos (26U)
7892#define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos)
7893#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
7894#define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos)
7895#define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos)
7896#define GPIO_PUPDR_PUPDR14_Pos (28U)
7897#define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos)
7898#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
7899#define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos)
7900#define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos)
7901#define GPIO_PUPDR_PUPDR15_Pos (30U)
7902#define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos)
7903#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
7904#define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos)
7905#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos)
7907/****************** Bits definition for GPIO_IDR register *******************/
7908#define GPIO_IDR_ID0_Pos (0U)
7909#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
7910#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
7911#define GPIO_IDR_ID1_Pos (1U)
7912#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
7913#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
7914#define GPIO_IDR_ID2_Pos (2U)
7915#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
7916#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
7917#define GPIO_IDR_ID3_Pos (3U)
7918#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
7919#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
7920#define GPIO_IDR_ID4_Pos (4U)
7921#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
7922#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
7923#define GPIO_IDR_ID5_Pos (5U)
7924#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
7925#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
7926#define GPIO_IDR_ID6_Pos (6U)
7927#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
7928#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
7929#define GPIO_IDR_ID7_Pos (7U)
7930#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
7931#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
7932#define GPIO_IDR_ID8_Pos (8U)
7933#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
7934#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
7935#define GPIO_IDR_ID9_Pos (9U)
7936#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
7937#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
7938#define GPIO_IDR_ID10_Pos (10U)
7939#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
7940#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
7941#define GPIO_IDR_ID11_Pos (11U)
7942#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
7943#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
7944#define GPIO_IDR_ID12_Pos (12U)
7945#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
7946#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
7947#define GPIO_IDR_ID13_Pos (13U)
7948#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
7949#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
7950#define GPIO_IDR_ID14_Pos (14U)
7951#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
7952#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
7953#define GPIO_IDR_ID15_Pos (15U)
7954#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
7955#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
7956
7957/* Legacy defines */
7958#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
7959#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
7960#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
7961#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
7962#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
7963#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
7964#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
7965#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
7966#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
7967#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
7968#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
7969#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
7970#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
7971#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
7972#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
7973#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
7974
7975/****************** Bits definition for GPIO_ODR register *******************/
7976#define GPIO_ODR_OD0_Pos (0U)
7977#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
7978#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
7979#define GPIO_ODR_OD1_Pos (1U)
7980#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
7981#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
7982#define GPIO_ODR_OD2_Pos (2U)
7983#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
7984#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
7985#define GPIO_ODR_OD3_Pos (3U)
7986#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
7987#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
7988#define GPIO_ODR_OD4_Pos (4U)
7989#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
7990#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
7991#define GPIO_ODR_OD5_Pos (5U)
7992#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
7993#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
7994#define GPIO_ODR_OD6_Pos (6U)
7995#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
7996#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
7997#define GPIO_ODR_OD7_Pos (7U)
7998#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
7999#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
8000#define GPIO_ODR_OD8_Pos (8U)
8001#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
8002#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
8003#define GPIO_ODR_OD9_Pos (9U)
8004#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
8005#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
8006#define GPIO_ODR_OD10_Pos (10U)
8007#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
8008#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
8009#define GPIO_ODR_OD11_Pos (11U)
8010#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
8011#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
8012#define GPIO_ODR_OD12_Pos (12U)
8013#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
8014#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
8015#define GPIO_ODR_OD13_Pos (13U)
8016#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
8017#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
8018#define GPIO_ODR_OD14_Pos (14U)
8019#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
8020#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
8021#define GPIO_ODR_OD15_Pos (15U)
8022#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
8023#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
8024
8025/* Legacy defines */
8026#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
8027#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
8028#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
8029#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
8030#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
8031#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
8032#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
8033#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
8034#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
8035#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
8036#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
8037#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
8038#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
8039#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
8040#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
8041#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
8042
8043/****************** Bits definition for GPIO_BSRR register ******************/
8044#define GPIO_BSRR_BS0_Pos (0U)
8045#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
8046#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
8047#define GPIO_BSRR_BS1_Pos (1U)
8048#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
8049#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
8050#define GPIO_BSRR_BS2_Pos (2U)
8051#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
8052#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
8053#define GPIO_BSRR_BS3_Pos (3U)
8054#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
8055#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
8056#define GPIO_BSRR_BS4_Pos (4U)
8057#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
8058#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
8059#define GPIO_BSRR_BS5_Pos (5U)
8060#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
8061#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
8062#define GPIO_BSRR_BS6_Pos (6U)
8063#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
8064#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
8065#define GPIO_BSRR_BS7_Pos (7U)
8066#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
8067#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
8068#define GPIO_BSRR_BS8_Pos (8U)
8069#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
8070#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
8071#define GPIO_BSRR_BS9_Pos (9U)
8072#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
8073#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
8074#define GPIO_BSRR_BS10_Pos (10U)
8075#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
8076#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
8077#define GPIO_BSRR_BS11_Pos (11U)
8078#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
8079#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
8080#define GPIO_BSRR_BS12_Pos (12U)
8081#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
8082#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
8083#define GPIO_BSRR_BS13_Pos (13U)
8084#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
8085#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
8086#define GPIO_BSRR_BS14_Pos (14U)
8087#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
8088#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
8089#define GPIO_BSRR_BS15_Pos (15U)
8090#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
8091#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
8092#define GPIO_BSRR_BR0_Pos (16U)
8093#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
8094#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
8095#define GPIO_BSRR_BR1_Pos (17U)
8096#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
8097#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
8098#define GPIO_BSRR_BR2_Pos (18U)
8099#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
8100#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
8101#define GPIO_BSRR_BR3_Pos (19U)
8102#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
8103#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
8104#define GPIO_BSRR_BR4_Pos (20U)
8105#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
8106#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
8107#define GPIO_BSRR_BR5_Pos (21U)
8108#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
8109#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
8110#define GPIO_BSRR_BR6_Pos (22U)
8111#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
8112#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
8113#define GPIO_BSRR_BR7_Pos (23U)
8114#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
8115#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
8116#define GPIO_BSRR_BR8_Pos (24U)
8117#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
8118#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
8119#define GPIO_BSRR_BR9_Pos (25U)
8120#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
8121#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
8122#define GPIO_BSRR_BR10_Pos (26U)
8123#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
8124#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
8125#define GPIO_BSRR_BR11_Pos (27U)
8126#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
8127#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
8128#define GPIO_BSRR_BR12_Pos (28U)
8129#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
8130#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
8131#define GPIO_BSRR_BR13_Pos (29U)
8132#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
8133#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
8134#define GPIO_BSRR_BR14_Pos (30U)
8135#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
8136#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
8137#define GPIO_BSRR_BR15_Pos (31U)
8138#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
8139#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
8140
8141/* Legacy defines */
8142#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
8143#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
8144#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
8145#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
8146#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
8147#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
8148#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
8149#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
8150#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
8151#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
8152#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
8153#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
8154#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
8155#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
8156#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
8157#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
8158#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
8159#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
8160#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
8161#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
8162#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
8163#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
8164#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
8165#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
8166#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
8167#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
8168#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
8169#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
8170#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
8171#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
8172#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
8173#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
8174
8175/****************** Bit definition for GPIO_LCKR register *********************/
8176#define GPIO_LCKR_LCK0_Pos (0U)
8177#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
8178#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
8179#define GPIO_LCKR_LCK1_Pos (1U)
8180#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
8181#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
8182#define GPIO_LCKR_LCK2_Pos (2U)
8183#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
8184#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
8185#define GPIO_LCKR_LCK3_Pos (3U)
8186#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
8187#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
8188#define GPIO_LCKR_LCK4_Pos (4U)
8189#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
8190#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
8191#define GPIO_LCKR_LCK5_Pos (5U)
8192#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
8193#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
8194#define GPIO_LCKR_LCK6_Pos (6U)
8195#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
8196#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
8197#define GPIO_LCKR_LCK7_Pos (7U)
8198#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
8199#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
8200#define GPIO_LCKR_LCK8_Pos (8U)
8201#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
8202#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
8203#define GPIO_LCKR_LCK9_Pos (9U)
8204#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
8205#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
8206#define GPIO_LCKR_LCK10_Pos (10U)
8207#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
8208#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
8209#define GPIO_LCKR_LCK11_Pos (11U)
8210#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
8211#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
8212#define GPIO_LCKR_LCK12_Pos (12U)
8213#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
8214#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
8215#define GPIO_LCKR_LCK13_Pos (13U)
8216#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
8217#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
8218#define GPIO_LCKR_LCK14_Pos (14U)
8219#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
8220#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
8221#define GPIO_LCKR_LCK15_Pos (15U)
8222#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
8223#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
8224#define GPIO_LCKR_LCKK_Pos (16U)
8225#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
8226#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
8227
8228/****************** Bit definition for GPIO_AFRL register *********************/
8229#define GPIO_AFRL_AFRL0_Pos (0U)
8230#define GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos)
8231#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk
8232#define GPIO_AFRL_AFRL0_0 (0x1UL << GPIO_AFRL_AFRL0_Pos)
8233#define GPIO_AFRL_AFRL0_1 (0x2UL << GPIO_AFRL_AFRL0_Pos)
8234#define GPIO_AFRL_AFRL0_2 (0x4UL << GPIO_AFRL_AFRL0_Pos)
8235#define GPIO_AFRL_AFRL0_3 (0x8UL << GPIO_AFRL_AFRL0_Pos)
8236#define GPIO_AFRL_AFRL1_Pos (4U)
8237#define GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos)
8238#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk
8239#define GPIO_AFRL_AFRL1_0 (0x1UL << GPIO_AFRL_AFRL1_Pos)
8240#define GPIO_AFRL_AFRL1_1 (0x2UL << GPIO_AFRL_AFRL1_Pos)
8241#define GPIO_AFRL_AFRL1_2 (0x4UL << GPIO_AFRL_AFRL1_Pos)
8242#define GPIO_AFRL_AFRL1_3 (0x8UL << GPIO_AFRL_AFRL1_Pos)
8243#define GPIO_AFRL_AFRL2_Pos (8U)
8244#define GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos)
8245#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk
8246#define GPIO_AFRL_AFRL2_0 (0x1UL << GPIO_AFRL_AFRL2_Pos)
8247#define GPIO_AFRL_AFRL2_1 (0x2UL << GPIO_AFRL_AFRL2_Pos)
8248#define GPIO_AFRL_AFRL2_2 (0x4UL << GPIO_AFRL_AFRL2_Pos)
8249#define GPIO_AFRL_AFRL2_3 (0x8UL << GPIO_AFRL_AFRL2_Pos)
8250#define GPIO_AFRL_AFRL3_Pos (12U)
8251#define GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos)
8252#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk
8253#define GPIO_AFRL_AFRL3_0 (0x1UL << GPIO_AFRL_AFRL3_Pos)
8254#define GPIO_AFRL_AFRL3_1 (0x2UL << GPIO_AFRL_AFRL3_Pos)
8255#define GPIO_AFRL_AFRL3_2 (0x4UL << GPIO_AFRL_AFRL3_Pos)
8256#define GPIO_AFRL_AFRL3_3 (0x8UL << GPIO_AFRL_AFRL3_Pos)
8257#define GPIO_AFRL_AFRL4_Pos (16U)
8258#define GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos)
8259#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk
8260#define GPIO_AFRL_AFRL4_0 (0x1UL << GPIO_AFRL_AFRL4_Pos)
8261#define GPIO_AFRL_AFRL4_1 (0x2UL << GPIO_AFRL_AFRL4_Pos)
8262#define GPIO_AFRL_AFRL4_2 (0x4UL << GPIO_AFRL_AFRL4_Pos)
8263#define GPIO_AFRL_AFRL4_3 (0x8UL << GPIO_AFRL_AFRL4_Pos)
8264#define GPIO_AFRL_AFRL5_Pos (20U)
8265#define GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos)
8266#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk
8267#define GPIO_AFRL_AFRL5_0 (0x1UL << GPIO_AFRL_AFRL5_Pos)
8268#define GPIO_AFRL_AFRL5_1 (0x2UL << GPIO_AFRL_AFRL5_Pos)
8269#define GPIO_AFRL_AFRL5_2 (0x4UL << GPIO_AFRL_AFRL5_Pos)
8270#define GPIO_AFRL_AFRL5_3 (0x8UL << GPIO_AFRL_AFRL5_Pos)
8271#define GPIO_AFRL_AFRL6_Pos (24U)
8272#define GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos)
8273#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk
8274#define GPIO_AFRL_AFRL6_0 (0x1UL << GPIO_AFRL_AFRL6_Pos)
8275#define GPIO_AFRL_AFRL6_1 (0x2UL << GPIO_AFRL_AFRL6_Pos)
8276#define GPIO_AFRL_AFRL6_2 (0x4UL << GPIO_AFRL_AFRL6_Pos)
8277#define GPIO_AFRL_AFRL6_3 (0x8UL << GPIO_AFRL_AFRL6_Pos)
8278#define GPIO_AFRL_AFRL7_Pos (28U)
8279#define GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos)
8280#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk
8281#define GPIO_AFRL_AFRL7_0 (0x1UL << GPIO_AFRL_AFRL7_Pos)
8282#define GPIO_AFRL_AFRL7_1 (0x2UL << GPIO_AFRL_AFRL7_Pos)
8283#define GPIO_AFRL_AFRL7_2 (0x4UL << GPIO_AFRL_AFRL7_Pos)
8284#define GPIO_AFRL_AFRL7_3 (0x8UL << GPIO_AFRL_AFRL7_Pos)
8286/****************** Bit definition for GPIO_AFRH register *********************/
8287#define GPIO_AFRH_AFRH0_Pos (0U)
8288#define GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos)
8289#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk
8290#define GPIO_AFRH_AFRH0_0 (0x1UL << GPIO_AFRH_AFRH0_Pos)
8291#define GPIO_AFRH_AFRH0_1 (0x2UL << GPIO_AFRH_AFRH0_Pos)
8292#define GPIO_AFRH_AFRH0_2 (0x4UL << GPIO_AFRH_AFRH0_Pos)
8293#define GPIO_AFRH_AFRH0_3 (0x8UL << GPIO_AFRH_AFRH0_Pos)
8294#define GPIO_AFRH_AFRH1_Pos (4U)
8295#define GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos)
8296#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk
8297#define GPIO_AFRH_AFRH1_0 (0x1UL << GPIO_AFRH_AFRH1_Pos)
8298#define GPIO_AFRH_AFRH1_1 (0x2UL << GPIO_AFRH_AFRH1_Pos)
8299#define GPIO_AFRH_AFRH1_2 (0x4UL << GPIO_AFRH_AFRH1_Pos)
8300#define GPIO_AFRH_AFRH1_3 (0x8UL << GPIO_AFRH_AFRH1_Pos)
8301#define GPIO_AFRH_AFRH2_Pos (8U)
8302#define GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos)
8303#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk
8304#define GPIO_AFRH_AFRH2_0 (0x1UL << GPIO_AFRH_AFRH2_Pos)
8305#define GPIO_AFRH_AFRH2_1 (0x2UL << GPIO_AFRH_AFRH2_Pos)
8306#define GPIO_AFRH_AFRH2_2 (0x4UL << GPIO_AFRH_AFRH2_Pos)
8307#define GPIO_AFRH_AFRH2_3 (0x8UL << GPIO_AFRH_AFRH2_Pos)
8308#define GPIO_AFRH_AFRH3_Pos (12U)
8309#define GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos)
8310#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk
8311#define GPIO_AFRH_AFRH3_0 (0x1UL << GPIO_AFRH_AFRH3_Pos)
8312#define GPIO_AFRH_AFRH3_1 (0x2UL << GPIO_AFRH_AFRH3_Pos)
8313#define GPIO_AFRH_AFRH3_2 (0x4UL << GPIO_AFRH_AFRH3_Pos)
8314#define GPIO_AFRH_AFRH3_3 (0x8UL << GPIO_AFRH_AFRH3_Pos)
8315#define GPIO_AFRH_AFRH4_Pos (16U)
8316#define GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos)
8317#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk
8318#define GPIO_AFRH_AFRH4_0 (0x1UL << GPIO_AFRH_AFRH4_Pos)
8319#define GPIO_AFRH_AFRH4_1 (0x2UL << GPIO_AFRH_AFRH4_Pos)
8320#define GPIO_AFRH_AFRH4_2 (0x4UL << GPIO_AFRH_AFRH4_Pos)
8321#define GPIO_AFRH_AFRH4_3 (0x8UL << GPIO_AFRH_AFRH4_Pos)
8322#define GPIO_AFRH_AFRH5_Pos (20U)
8323#define GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos)
8324#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk
8325#define GPIO_AFRH_AFRH5_0 (0x1UL << GPIO_AFRH_AFRH5_Pos)
8326#define GPIO_AFRH_AFRH5_1 (0x2UL << GPIO_AFRH_AFRH5_Pos)
8327#define GPIO_AFRH_AFRH5_2 (0x4UL << GPIO_AFRH_AFRH5_Pos)
8328#define GPIO_AFRH_AFRH5_3 (0x8UL << GPIO_AFRH_AFRH5_Pos)
8329#define GPIO_AFRH_AFRH6_Pos (24U)
8330#define GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos)
8331#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk
8332#define GPIO_AFRH_AFRH6_0 (0x1UL << GPIO_AFRH_AFRH6_Pos)
8333#define GPIO_AFRH_AFRH6_1 (0x2UL << GPIO_AFRH_AFRH6_Pos)
8334#define GPIO_AFRH_AFRH6_2 (0x4UL << GPIO_AFRH_AFRH6_Pos)
8335#define GPIO_AFRH_AFRH6_3 (0x8UL << GPIO_AFRH_AFRH6_Pos)
8336#define GPIO_AFRH_AFRH7_Pos (28U)
8337#define GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos)
8338#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk
8339#define GPIO_AFRH_AFRH7_0 (0x1UL << GPIO_AFRH_AFRH7_Pos)
8340#define GPIO_AFRH_AFRH7_1 (0x2UL << GPIO_AFRH_AFRH7_Pos)
8341#define GPIO_AFRH_AFRH7_2 (0x4UL << GPIO_AFRH_AFRH7_Pos)
8342#define GPIO_AFRH_AFRH7_3 (0x8UL << GPIO_AFRH_AFRH7_Pos)
8345/******************************************************************************/
8346/* */
8347/* Inter-integrated Circuit Interface (I2C) */
8348/* */
8349/******************************************************************************/
8350/******************* Bit definition for I2C_CR1 register *******************/
8351#define I2C_CR1_PE_Pos (0U)
8352#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
8353#define I2C_CR1_PE I2C_CR1_PE_Msk
8354#define I2C_CR1_TXIE_Pos (1U)
8355#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
8356#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
8357#define I2C_CR1_RXIE_Pos (2U)
8358#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
8359#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
8360#define I2C_CR1_ADDRIE_Pos (3U)
8361#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
8362#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
8363#define I2C_CR1_NACKIE_Pos (4U)
8364#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
8365#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
8366#define I2C_CR1_STOPIE_Pos (5U)
8367#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
8368#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
8369#define I2C_CR1_TCIE_Pos (6U)
8370#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
8371#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
8372#define I2C_CR1_ERRIE_Pos (7U)
8373#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
8374#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
8375#define I2C_CR1_DNF_Pos (8U)
8376#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
8377#define I2C_CR1_DNF I2C_CR1_DNF_Msk
8378#define I2C_CR1_ANFOFF_Pos (12U)
8379#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
8380#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
8381#define I2C_CR1_TXDMAEN_Pos (14U)
8382#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
8383#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
8384#define I2C_CR1_RXDMAEN_Pos (15U)
8385#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
8386#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
8387#define I2C_CR1_SBC_Pos (16U)
8388#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
8389#define I2C_CR1_SBC I2C_CR1_SBC_Msk
8390#define I2C_CR1_NOSTRETCH_Pos (17U)
8391#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
8392#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
8393#define I2C_CR1_GCEN_Pos (19U)
8394#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
8395#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
8396#define I2C_CR1_SMBHEN_Pos (20U)
8397#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
8398#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
8399#define I2C_CR1_SMBDEN_Pos (21U)
8400#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
8401#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
8402#define I2C_CR1_ALERTEN_Pos (22U)
8403#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
8404#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
8405#define I2C_CR1_PECEN_Pos (23U)
8406#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
8407#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
8410/****************** Bit definition for I2C_CR2 register ********************/
8411#define I2C_CR2_SADD_Pos (0U)
8412#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
8413#define I2C_CR2_SADD I2C_CR2_SADD_Msk
8414#define I2C_CR2_RD_WRN_Pos (10U)
8415#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
8416#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
8417#define I2C_CR2_ADD10_Pos (11U)
8418#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
8419#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
8420#define I2C_CR2_HEAD10R_Pos (12U)
8421#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
8422#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
8423#define I2C_CR2_START_Pos (13U)
8424#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
8425#define I2C_CR2_START I2C_CR2_START_Msk
8426#define I2C_CR2_STOP_Pos (14U)
8427#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
8428#define I2C_CR2_STOP I2C_CR2_STOP_Msk
8429#define I2C_CR2_NACK_Pos (15U)
8430#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
8431#define I2C_CR2_NACK I2C_CR2_NACK_Msk
8432#define I2C_CR2_NBYTES_Pos (16U)
8433#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
8434#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
8435#define I2C_CR2_RELOAD_Pos (24U)
8436#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
8437#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
8438#define I2C_CR2_AUTOEND_Pos (25U)
8439#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
8440#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
8441#define I2C_CR2_PECBYTE_Pos (26U)
8442#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
8443#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
8445/******************* Bit definition for I2C_OAR1 register ******************/
8446#define I2C_OAR1_OA1_Pos (0U)
8447#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
8448#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
8449#define I2C_OAR1_OA1MODE_Pos (10U)
8450#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
8451#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
8452#define I2C_OAR1_OA1EN_Pos (15U)
8453#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
8454#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
8456/******************* Bit definition for I2C_OAR2 register ******************/
8457#define I2C_OAR2_OA2_Pos (1U)
8458#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
8459#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
8460#define I2C_OAR2_OA2MSK_Pos (8U)
8461#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
8462#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
8463#define I2C_OAR2_OA2NOMASK 0x00000000U
8464#define I2C_OAR2_OA2MASK01_Pos (8U)
8465#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
8466#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
8467#define I2C_OAR2_OA2MASK02_Pos (9U)
8468#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
8469#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
8470#define I2C_OAR2_OA2MASK03_Pos (8U)
8471#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
8472#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
8473#define I2C_OAR2_OA2MASK04_Pos (10U)
8474#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
8475#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
8476#define I2C_OAR2_OA2MASK05_Pos (8U)
8477#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
8478#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
8479#define I2C_OAR2_OA2MASK06_Pos (9U)
8480#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
8481#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
8482#define I2C_OAR2_OA2MASK07_Pos (8U)
8483#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
8484#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
8485#define I2C_OAR2_OA2EN_Pos (15U)
8486#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
8487#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
8489/******************* Bit definition for I2C_TIMINGR register *******************/
8490#define I2C_TIMINGR_SCLL_Pos (0U)
8491#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
8492#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
8493#define I2C_TIMINGR_SCLH_Pos (8U)
8494#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
8495#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
8496#define I2C_TIMINGR_SDADEL_Pos (16U)
8497#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
8498#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
8499#define I2C_TIMINGR_SCLDEL_Pos (20U)
8500#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
8501#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
8502#define I2C_TIMINGR_PRESC_Pos (28U)
8503#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
8504#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
8506/******************* Bit definition for I2C_TIMEOUTR register *******************/
8507#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
8508#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
8509#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
8510#define I2C_TIMEOUTR_TIDLE_Pos (12U)
8511#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
8512#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
8513#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
8514#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
8515#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
8516#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
8517#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
8518#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
8519#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
8520#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
8521#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
8523/****************** Bit definition for I2C_ISR register *********************/
8524#define I2C_ISR_TXE_Pos (0U)
8525#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
8526#define I2C_ISR_TXE I2C_ISR_TXE_Msk
8527#define I2C_ISR_TXIS_Pos (1U)
8528#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
8529#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
8530#define I2C_ISR_RXNE_Pos (2U)
8531#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
8532#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
8533#define I2C_ISR_ADDR_Pos (3U)
8534#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
8535#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
8536#define I2C_ISR_NACKF_Pos (4U)
8537#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
8538#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
8539#define I2C_ISR_STOPF_Pos (5U)
8540#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
8541#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
8542#define I2C_ISR_TC_Pos (6U)
8543#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
8544#define I2C_ISR_TC I2C_ISR_TC_Msk
8545#define I2C_ISR_TCR_Pos (7U)
8546#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
8547#define I2C_ISR_TCR I2C_ISR_TCR_Msk
8548#define I2C_ISR_BERR_Pos (8U)
8549#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
8550#define I2C_ISR_BERR I2C_ISR_BERR_Msk
8551#define I2C_ISR_ARLO_Pos (9U)
8552#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
8553#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
8554#define I2C_ISR_OVR_Pos (10U)
8555#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
8556#define I2C_ISR_OVR I2C_ISR_OVR_Msk
8557#define I2C_ISR_PECERR_Pos (11U)
8558#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
8559#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
8560#define I2C_ISR_TIMEOUT_Pos (12U)
8561#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
8562#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
8563#define I2C_ISR_ALERT_Pos (13U)
8564#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
8565#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
8566#define I2C_ISR_BUSY_Pos (15U)
8567#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
8568#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
8569#define I2C_ISR_DIR_Pos (16U)
8570#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
8571#define I2C_ISR_DIR I2C_ISR_DIR_Msk
8572#define I2C_ISR_ADDCODE_Pos (17U)
8573#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
8574#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
8576/****************** Bit definition for I2C_ICR register *********************/
8577#define I2C_ICR_ADDRCF_Pos (3U)
8578#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
8579#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
8580#define I2C_ICR_NACKCF_Pos (4U)
8581#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
8582#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
8583#define I2C_ICR_STOPCF_Pos (5U)
8584#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
8585#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
8586#define I2C_ICR_BERRCF_Pos (8U)
8587#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
8588#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
8589#define I2C_ICR_ARLOCF_Pos (9U)
8590#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
8591#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
8592#define I2C_ICR_OVRCF_Pos (10U)
8593#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
8594#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
8595#define I2C_ICR_PECCF_Pos (11U)
8596#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
8597#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
8598#define I2C_ICR_TIMOUTCF_Pos (12U)
8599#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
8600#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
8601#define I2C_ICR_ALERTCF_Pos (13U)
8602#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
8603#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
8605/****************** Bit definition for I2C_PECR register *********************/
8606#define I2C_PECR_PEC_Pos (0U)
8607#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
8608#define I2C_PECR_PEC I2C_PECR_PEC_Msk
8610/****************** Bit definition for I2C_RXDR register *********************/
8611#define I2C_RXDR_RXDATA_Pos (0U)
8612#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
8613#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
8615/****************** Bit definition for I2C_TXDR register *********************/
8616#define I2C_TXDR_TXDATA_Pos (0U)
8617#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
8618#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
8621/******************************************************************************/
8622/* */
8623/* Independent WATCHDOG */
8624/* */
8625/******************************************************************************/
8626/******************* Bit definition for IWDG_KR register ********************/
8627#define IWDG_KR_KEY_Pos (0U)
8628#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
8629#define IWDG_KR_KEY IWDG_KR_KEY_Msk
8631/******************* Bit definition for IWDG_PR register ********************/
8632#define IWDG_PR_PR_Pos (0U)
8633#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
8634#define IWDG_PR_PR IWDG_PR_PR_Msk
8635#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
8636#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
8637#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
8639/******************* Bit definition for IWDG_RLR register *******************/
8640#define IWDG_RLR_RL_Pos (0U)
8641#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
8642#define IWDG_RLR_RL IWDG_RLR_RL_Msk
8644/******************* Bit definition for IWDG_SR register ********************/
8645#define IWDG_SR_PVU_Pos (0U)
8646#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
8647#define IWDG_SR_PVU IWDG_SR_PVU_Msk
8648#define IWDG_SR_RVU_Pos (1U)
8649#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
8650#define IWDG_SR_RVU IWDG_SR_RVU_Msk
8651#define IWDG_SR_WVU_Pos (2U)
8652#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
8653#define IWDG_SR_WVU IWDG_SR_WVU_Msk
8655/******************* Bit definition for IWDG_KR register ********************/
8656#define IWDG_WINR_WIN_Pos (0U)
8657#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
8658#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
8661/******************************************************************************/
8662/* */
8663/* Power Control */
8664/* */
8665/******************************************************************************/
8666/******************** Bit definition for PWR_CR1 register ********************/
8667#define PWR_CR1_LPDS_Pos (0U)
8668#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos)
8669#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk
8670#define PWR_CR1_PDDS_Pos (1U)
8671#define PWR_CR1_PDDS_Msk (0x1UL << PWR_CR1_PDDS_Pos)
8672#define PWR_CR1_PDDS PWR_CR1_PDDS_Msk
8673#define PWR_CR1_CSBF_Pos (3U)
8674#define PWR_CR1_CSBF_Msk (0x1UL << PWR_CR1_CSBF_Pos)
8675#define PWR_CR1_CSBF PWR_CR1_CSBF_Msk
8676#define PWR_CR1_PVDE_Pos (4U)
8677#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos)
8678#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk
8679#define PWR_CR1_PLS_Pos (5U)
8680#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos)
8681#define PWR_CR1_PLS PWR_CR1_PLS_Msk
8682#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos)
8683#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos)
8684#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos)
8687#define PWR_CR1_PLS_LEV0 0x00000000U
8688#define PWR_CR1_PLS_LEV1_Pos (5U)
8689#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos)
8690#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk
8691#define PWR_CR1_PLS_LEV2_Pos (6U)
8692#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos)
8693#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk
8694#define PWR_CR1_PLS_LEV3_Pos (5U)
8695#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos)
8696#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk
8697#define PWR_CR1_PLS_LEV4_Pos (7U)
8698#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos)
8699#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk
8700#define PWR_CR1_PLS_LEV5_Pos (5U)
8701#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos)
8702#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk
8703#define PWR_CR1_PLS_LEV6_Pos (6U)
8704#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos)
8705#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk
8706#define PWR_CR1_PLS_LEV7_Pos (5U)
8707#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos)
8708#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk
8709#define PWR_CR1_DBP_Pos (8U)
8710#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
8711#define PWR_CR1_DBP PWR_CR1_DBP_Msk
8712#define PWR_CR1_FPDS_Pos (9U)
8713#define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos)
8714#define PWR_CR1_FPDS PWR_CR1_FPDS_Msk
8715#define PWR_CR1_LPUDS_Pos (10U)
8716#define PWR_CR1_LPUDS_Msk (0x1UL << PWR_CR1_LPUDS_Pos)
8717#define PWR_CR1_LPUDS PWR_CR1_LPUDS_Msk
8718#define PWR_CR1_MRUDS_Pos (11U)
8719#define PWR_CR1_MRUDS_Msk (0x1UL << PWR_CR1_MRUDS_Pos)
8720#define PWR_CR1_MRUDS PWR_CR1_MRUDS_Msk
8721#define PWR_CR1_ADCDC1_Pos (13U)
8722#define PWR_CR1_ADCDC1_Msk (0x1UL << PWR_CR1_ADCDC1_Pos)
8723#define PWR_CR1_ADCDC1 PWR_CR1_ADCDC1_Msk
8724#define PWR_CR1_VOS_Pos (14U)
8725#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos)
8726#define PWR_CR1_VOS PWR_CR1_VOS_Msk
8727#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos)
8728#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos)
8729#define PWR_CR1_ODEN_Pos (16U)
8730#define PWR_CR1_ODEN_Msk (0x1UL << PWR_CR1_ODEN_Pos)
8731#define PWR_CR1_ODEN PWR_CR1_ODEN_Msk
8732#define PWR_CR1_ODSWEN_Pos (17U)
8733#define PWR_CR1_ODSWEN_Msk (0x1UL << PWR_CR1_ODSWEN_Pos)
8734#define PWR_CR1_ODSWEN PWR_CR1_ODSWEN_Msk
8735#define PWR_CR1_UDEN_Pos (18U)
8736#define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos)
8737#define PWR_CR1_UDEN PWR_CR1_UDEN_Msk
8738#define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos)
8739#define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos)
8741/******************* Bit definition for PWR_CSR1 register ********************/
8742#define PWR_CSR1_WUIF_Pos (0U)
8743#define PWR_CSR1_WUIF_Msk (0x1UL << PWR_CSR1_WUIF_Pos)
8744#define PWR_CSR1_WUIF PWR_CSR1_WUIF_Msk
8745#define PWR_CSR1_SBF_Pos (1U)
8746#define PWR_CSR1_SBF_Msk (0x1UL << PWR_CSR1_SBF_Pos)
8747#define PWR_CSR1_SBF PWR_CSR1_SBF_Msk
8748#define PWR_CSR1_PVDO_Pos (2U)
8749#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos)
8750#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk
8751#define PWR_CSR1_BRR_Pos (3U)
8752#define PWR_CSR1_BRR_Msk (0x1UL << PWR_CSR1_BRR_Pos)
8753#define PWR_CSR1_BRR PWR_CSR1_BRR_Msk
8754#define PWR_CSR1_EIWUP_Pos (8U)
8755#define PWR_CSR1_EIWUP_Msk (0x1UL << PWR_CSR1_EIWUP_Pos)
8756#define PWR_CSR1_EIWUP PWR_CSR1_EIWUP_Msk
8757#define PWR_CSR1_BRE_Pos (9U)
8758#define PWR_CSR1_BRE_Msk (0x1UL << PWR_CSR1_BRE_Pos)
8759#define PWR_CSR1_BRE PWR_CSR1_BRE_Msk
8760#define PWR_CSR1_VOSRDY_Pos (14U)
8761#define PWR_CSR1_VOSRDY_Msk (0x1UL << PWR_CSR1_VOSRDY_Pos)
8762#define PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY_Msk
8763#define PWR_CSR1_ODRDY_Pos (16U)
8764#define PWR_CSR1_ODRDY_Msk (0x1UL << PWR_CSR1_ODRDY_Pos)
8765#define PWR_CSR1_ODRDY PWR_CSR1_ODRDY_Msk
8766#define PWR_CSR1_ODSWRDY_Pos (17U)
8767#define PWR_CSR1_ODSWRDY_Msk (0x1UL << PWR_CSR1_ODSWRDY_Pos)
8768#define PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY_Msk
8769#define PWR_CSR1_UDRDY_Pos (18U)
8770#define PWR_CSR1_UDRDY_Msk (0x3UL << PWR_CSR1_UDRDY_Pos)
8771#define PWR_CSR1_UDRDY PWR_CSR1_UDRDY_Msk
8774/******************** Bit definition for PWR_CR2 register ********************/
8775#define PWR_CR2_CWUPF1_Pos (0U)
8776#define PWR_CR2_CWUPF1_Msk (0x1UL << PWR_CR2_CWUPF1_Pos)
8777#define PWR_CR2_CWUPF1 PWR_CR2_CWUPF1_Msk
8778#define PWR_CR2_CWUPF2_Pos (1U)
8779#define PWR_CR2_CWUPF2_Msk (0x1UL << PWR_CR2_CWUPF2_Pos)
8780#define PWR_CR2_CWUPF2 PWR_CR2_CWUPF2_Msk
8781#define PWR_CR2_CWUPF3_Pos (2U)
8782#define PWR_CR2_CWUPF3_Msk (0x1UL << PWR_CR2_CWUPF3_Pos)
8783#define PWR_CR2_CWUPF3 PWR_CR2_CWUPF3_Msk
8784#define PWR_CR2_CWUPF4_Pos (3U)
8785#define PWR_CR2_CWUPF4_Msk (0x1UL << PWR_CR2_CWUPF4_Pos)
8786#define PWR_CR2_CWUPF4 PWR_CR2_CWUPF4_Msk
8787#define PWR_CR2_CWUPF5_Pos (4U)
8788#define PWR_CR2_CWUPF5_Msk (0x1UL << PWR_CR2_CWUPF5_Pos)
8789#define PWR_CR2_CWUPF5 PWR_CR2_CWUPF5_Msk
8790#define PWR_CR2_CWUPF6_Pos (5U)
8791#define PWR_CR2_CWUPF6_Msk (0x1UL << PWR_CR2_CWUPF6_Pos)
8792#define PWR_CR2_CWUPF6 PWR_CR2_CWUPF6_Msk
8793#define PWR_CR2_WUPP1_Pos (8U)
8794#define PWR_CR2_WUPP1_Msk (0x1UL << PWR_CR2_WUPP1_Pos)
8795#define PWR_CR2_WUPP1 PWR_CR2_WUPP1_Msk
8796#define PWR_CR2_WUPP2_Pos (9U)
8797#define PWR_CR2_WUPP2_Msk (0x1UL << PWR_CR2_WUPP2_Pos)
8798#define PWR_CR2_WUPP2 PWR_CR2_WUPP2_Msk
8799#define PWR_CR2_WUPP3_Pos (10U)
8800#define PWR_CR2_WUPP3_Msk (0x1UL << PWR_CR2_WUPP3_Pos)
8801#define PWR_CR2_WUPP3 PWR_CR2_WUPP3_Msk
8802#define PWR_CR2_WUPP4_Pos (11U)
8803#define PWR_CR2_WUPP4_Msk (0x1UL << PWR_CR2_WUPP4_Pos)
8804#define PWR_CR2_WUPP4 PWR_CR2_WUPP4_Msk
8805#define PWR_CR2_WUPP5_Pos (12U)
8806#define PWR_CR2_WUPP5_Msk (0x1UL << PWR_CR2_WUPP5_Pos)
8807#define PWR_CR2_WUPP5 PWR_CR2_WUPP5_Msk
8808#define PWR_CR2_WUPP6_Pos (13U)
8809#define PWR_CR2_WUPP6_Msk (0x1UL << PWR_CR2_WUPP6_Pos)
8810#define PWR_CR2_WUPP6 PWR_CR2_WUPP6_Msk
8812/******************* Bit definition for PWR_CSR2 register ********************/
8813#define PWR_CSR2_WUPF1_Pos (0U)
8814#define PWR_CSR2_WUPF1_Msk (0x1UL << PWR_CSR2_WUPF1_Pos)
8815#define PWR_CSR2_WUPF1 PWR_CSR2_WUPF1_Msk
8816#define PWR_CSR2_WUPF2_Pos (1U)
8817#define PWR_CSR2_WUPF2_Msk (0x1UL << PWR_CSR2_WUPF2_Pos)
8818#define PWR_CSR2_WUPF2 PWR_CSR2_WUPF2_Msk
8819#define PWR_CSR2_WUPF3_Pos (2U)
8820#define PWR_CSR2_WUPF3_Msk (0x1UL << PWR_CSR2_WUPF3_Pos)
8821#define PWR_CSR2_WUPF3 PWR_CSR2_WUPF3_Msk
8822#define PWR_CSR2_WUPF4_Pos (3U)
8823#define PWR_CSR2_WUPF4_Msk (0x1UL << PWR_CSR2_WUPF4_Pos)
8824#define PWR_CSR2_WUPF4 PWR_CSR2_WUPF4_Msk
8825#define PWR_CSR2_WUPF5_Pos (4U)
8826#define PWR_CSR2_WUPF5_Msk (0x1UL << PWR_CSR2_WUPF5_Pos)
8827#define PWR_CSR2_WUPF5 PWR_CSR2_WUPF5_Msk
8828#define PWR_CSR2_WUPF6_Pos (5U)
8829#define PWR_CSR2_WUPF6_Msk (0x1UL << PWR_CSR2_WUPF6_Pos)
8830#define PWR_CSR2_WUPF6 PWR_CSR2_WUPF6_Msk
8831#define PWR_CSR2_EWUP1_Pos (8U)
8832#define PWR_CSR2_EWUP1_Msk (0x1UL << PWR_CSR2_EWUP1_Pos)
8833#define PWR_CSR2_EWUP1 PWR_CSR2_EWUP1_Msk
8834#define PWR_CSR2_EWUP2_Pos (9U)
8835#define PWR_CSR2_EWUP2_Msk (0x1UL << PWR_CSR2_EWUP2_Pos)
8836#define PWR_CSR2_EWUP2 PWR_CSR2_EWUP2_Msk
8837#define PWR_CSR2_EWUP3_Pos (10U)
8838#define PWR_CSR2_EWUP3_Msk (0x1UL << PWR_CSR2_EWUP3_Pos)
8839#define PWR_CSR2_EWUP3 PWR_CSR2_EWUP3_Msk
8840#define PWR_CSR2_EWUP4_Pos (11U)
8841#define PWR_CSR2_EWUP4_Msk (0x1UL << PWR_CSR2_EWUP4_Pos)
8842#define PWR_CSR2_EWUP4 PWR_CSR2_EWUP4_Msk
8843#define PWR_CSR2_EWUP5_Pos (12U)
8844#define PWR_CSR2_EWUP5_Msk (0x1UL << PWR_CSR2_EWUP5_Pos)
8845#define PWR_CSR2_EWUP5 PWR_CSR2_EWUP5_Msk
8846#define PWR_CSR2_EWUP6_Pos (13U)
8847#define PWR_CSR2_EWUP6_Msk (0x1UL << PWR_CSR2_EWUP6_Pos)
8848#define PWR_CSR2_EWUP6 PWR_CSR2_EWUP6_Msk
8850/******************************************************************************/
8851/* */
8852/* QUADSPI */
8853/* */
8854/******************************************************************************/
8855/***************** Bit definition for QUADSPI_CR register *******************/
8856#define QUADSPI_CR_EN_Pos (0U)
8857#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
8858#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
8859#define QUADSPI_CR_ABORT_Pos (1U)
8860#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
8861#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
8862#define QUADSPI_CR_DMAEN_Pos (2U)
8863#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
8864#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
8865#define QUADSPI_CR_TCEN_Pos (3U)
8866#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
8867#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
8868#define QUADSPI_CR_SSHIFT_Pos (4U)
8869#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
8870#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
8871#define QUADSPI_CR_DFM_Pos (6U)
8872#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
8873#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
8874#define QUADSPI_CR_FSEL_Pos (7U)
8875#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
8876#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
8877#define QUADSPI_CR_FTHRES_Pos (8U)
8878#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
8879#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
8880#define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos)
8881#define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos)
8882#define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos)
8883#define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos)
8884#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
8885#define QUADSPI_CR_TEIE_Pos (16U)
8886#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
8887#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
8888#define QUADSPI_CR_TCIE_Pos (17U)
8889#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
8890#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
8891#define QUADSPI_CR_FTIE_Pos (18U)
8892#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
8893#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
8894#define QUADSPI_CR_SMIE_Pos (19U)
8895#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
8896#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
8897#define QUADSPI_CR_TOIE_Pos (20U)
8898#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
8899#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
8900#define QUADSPI_CR_APMS_Pos (22U)
8901#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
8902#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
8903#define QUADSPI_CR_PMM_Pos (23U)
8904#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
8905#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
8906#define QUADSPI_CR_PRESCALER_Pos (24U)
8907#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
8908#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
8909#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
8910#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
8911#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
8912#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
8913#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
8914#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
8915#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
8916#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
8918/***************** Bit definition for QUADSPI_DCR register ******************/
8919#define QUADSPI_DCR_CKMODE_Pos (0U)
8920#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
8921#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
8922#define QUADSPI_DCR_CSHT_Pos (8U)
8923#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
8924#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
8925#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
8926#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
8927#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
8928#define QUADSPI_DCR_FSIZE_Pos (16U)
8929#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
8930#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
8931#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
8932#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
8933#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
8934#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
8935#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
8937/****************** Bit definition for QUADSPI_SR register *******************/
8938#define QUADSPI_SR_TEF_Pos (0U)
8939#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
8940#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
8941#define QUADSPI_SR_TCF_Pos (1U)
8942#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
8943#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
8944#define QUADSPI_SR_FTF_Pos (2U)
8945#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
8946#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
8947#define QUADSPI_SR_SMF_Pos (3U)
8948#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
8949#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
8950#define QUADSPI_SR_TOF_Pos (4U)
8951#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
8952#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
8953#define QUADSPI_SR_BUSY_Pos (5U)
8954#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
8955#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
8956#define QUADSPI_SR_FLEVEL_Pos (8U)
8957#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
8958#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
8959#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
8960#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
8961#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
8962#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
8963#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
8964#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
8966/****************** Bit definition for QUADSPI_FCR register ******************/
8967#define QUADSPI_FCR_CTEF_Pos (0U)
8968#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
8969#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
8970#define QUADSPI_FCR_CTCF_Pos (1U)
8971#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
8972#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
8973#define QUADSPI_FCR_CSMF_Pos (3U)
8974#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
8975#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
8976#define QUADSPI_FCR_CTOF_Pos (4U)
8977#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
8978#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
8980/****************** Bit definition for QUADSPI_DLR register ******************/
8981#define QUADSPI_DLR_DL_Pos (0U)
8982#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
8983#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
8985/****************** Bit definition for QUADSPI_CCR register ******************/
8986#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
8987#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
8988#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
8989#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
8990#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
8991#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
8992#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
8993#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
8994#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
8995#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
8996#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
8997#define QUADSPI_CCR_IMODE_Pos (8U)
8998#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
8999#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
9000#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
9001#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
9002#define QUADSPI_CCR_ADMODE_Pos (10U)
9003#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
9004#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
9005#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
9006#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
9007#define QUADSPI_CCR_ADSIZE_Pos (12U)
9008#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
9009#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
9010#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
9011#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
9012#define QUADSPI_CCR_ABMODE_Pos (14U)
9013#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
9014#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
9015#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
9016#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
9017#define QUADSPI_CCR_ABSIZE_Pos (16U)
9018#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
9019#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
9020#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
9021#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
9022#define QUADSPI_CCR_DCYC_Pos (18U)
9023#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
9024#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
9025#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
9026#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
9027#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
9028#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
9029#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
9030#define QUADSPI_CCR_DMODE_Pos (24U)
9031#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
9032#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
9033#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
9034#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
9035#define QUADSPI_CCR_FMODE_Pos (26U)
9036#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
9037#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
9038#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
9039#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
9040#define QUADSPI_CCR_SIOO_Pos (28U)
9041#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
9042#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
9043#define QUADSPI_CCR_DHHC_Pos (30U)
9044#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
9045#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
9046#define QUADSPI_CCR_DDRM_Pos (31U)
9047#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
9048#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
9049/****************** Bit definition for QUADSPI_AR register *******************/
9050#define QUADSPI_AR_ADDRESS_Pos (0U)
9051#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
9052#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
9054/****************** Bit definition for QUADSPI_ABR register ******************/
9055#define QUADSPI_ABR_ALTERNATE_Pos (0U)
9056#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
9057#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
9059/****************** Bit definition for QUADSPI_DR register *******************/
9060#define QUADSPI_DR_DATA_Pos (0U)
9061#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
9062#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
9064/****************** Bit definition for QUADSPI_PSMKR register ****************/
9065#define QUADSPI_PSMKR_MASK_Pos (0U)
9066#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
9067#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
9069/****************** Bit definition for QUADSPI_PSMAR register ****************/
9070#define QUADSPI_PSMAR_MATCH_Pos (0U)
9071#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
9072#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
9074/****************** Bit definition for QUADSPI_PIR register *****************/
9075#define QUADSPI_PIR_INTERVAL_Pos (0U)
9076#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
9077#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
9079/****************** Bit definition for QUADSPI_LPTR register *****************/
9080#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
9081#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
9082#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
9084/******************************************************************************/
9085/* */
9086/* Reset and Clock Control */
9087/* */
9088/******************************************************************************/
9089/******************** Bit definition for RCC_CR register ********************/
9090#define RCC_CR_HSION_Pos (0U)
9091#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
9092#define RCC_CR_HSION RCC_CR_HSION_Msk
9093#define RCC_CR_HSIRDY_Pos (1U)
9094#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
9095#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
9096#define RCC_CR_HSITRIM_Pos (3U)
9097#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
9098#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
9099#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos)
9100#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos)
9101#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos)
9102#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos)
9103#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos)
9104#define RCC_CR_HSICAL_Pos (8U)
9105#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
9106#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
9107#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos)
9108#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos)
9109#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos)
9110#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos)
9111#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos)
9112#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos)
9113#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos)
9114#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos)
9115#define RCC_CR_HSEON_Pos (16U)
9116#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
9117#define RCC_CR_HSEON RCC_CR_HSEON_Msk
9118#define RCC_CR_HSERDY_Pos (17U)
9119#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
9120#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
9121#define RCC_CR_HSEBYP_Pos (18U)
9122#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
9123#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
9124#define RCC_CR_CSSON_Pos (19U)
9125#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
9126#define RCC_CR_CSSON RCC_CR_CSSON_Msk
9127#define RCC_CR_PLLON_Pos (24U)
9128#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
9129#define RCC_CR_PLLON RCC_CR_PLLON_Msk
9130#define RCC_CR_PLLRDY_Pos (25U)
9131#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
9132#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
9133#define RCC_CR_PLLI2SON_Pos (26U)
9134#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos)
9135#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
9136#define RCC_CR_PLLI2SRDY_Pos (27U)
9137#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos)
9138#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
9139#define RCC_CR_PLLSAION_Pos (28U)
9140#define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos)
9141#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
9142#define RCC_CR_PLLSAIRDY_Pos (29U)
9143#define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos)
9144#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
9145
9146/******************** Bit definition for RCC_PLLCFGR register ***************/
9147#define RCC_PLLCFGR_PLLM_Pos (0U)
9148#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos)
9149#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
9150#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos)
9151#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos)
9152#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos)
9153#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos)
9154#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos)
9155#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos)
9156#define RCC_PLLCFGR_PLLN_Pos (6U)
9157#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)
9158#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
9159#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos)
9160#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos)
9161#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos)
9162#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos)
9163#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos)
9164#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos)
9165#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos)
9166#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos)
9167#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos)
9168#define RCC_PLLCFGR_PLLP_Pos (16U)
9169#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos)
9170#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
9171#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos)
9172#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos)
9173#define RCC_PLLCFGR_PLLSRC_Pos (22U)
9174#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)
9175#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
9176#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
9177#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)
9178#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
9179#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
9180#define RCC_PLLCFGR_PLLQ_Pos (24U)
9181#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos)
9182#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
9183#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)
9184#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)
9185#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)
9186#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)
9189/******************** Bit definition for RCC_CFGR register ******************/
9191#define RCC_CFGR_SW_Pos (0U)
9192#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
9193#define RCC_CFGR_SW RCC_CFGR_SW_Msk
9194#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
9195#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
9196#define RCC_CFGR_SW_HSI 0x00000000U
9197#define RCC_CFGR_SW_HSE 0x00000001U
9198#define RCC_CFGR_SW_PLL 0x00000002U
9201#define RCC_CFGR_SWS_Pos (2U)
9202#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
9203#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
9204#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
9205#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
9206#define RCC_CFGR_SWS_HSI 0x00000000U
9207#define RCC_CFGR_SWS_HSE 0x00000004U
9208#define RCC_CFGR_SWS_PLL 0x00000008U
9211#define RCC_CFGR_HPRE_Pos (4U)
9212#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
9213#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
9214#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
9215#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
9216#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
9217#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
9219#define RCC_CFGR_HPRE_DIV1 0x00000000U
9220#define RCC_CFGR_HPRE_DIV2 0x00000080U
9221#define RCC_CFGR_HPRE_DIV4 0x00000090U
9222#define RCC_CFGR_HPRE_DIV8 0x000000A0U
9223#define RCC_CFGR_HPRE_DIV16 0x000000B0U
9224#define RCC_CFGR_HPRE_DIV64 0x000000C0U
9225#define RCC_CFGR_HPRE_DIV128 0x000000D0U
9226#define RCC_CFGR_HPRE_DIV256 0x000000E0U
9227#define RCC_CFGR_HPRE_DIV512 0x000000F0U
9230#define RCC_CFGR_PPRE1_Pos (10U)
9231#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
9232#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
9233#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
9234#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
9235#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
9237#define RCC_CFGR_PPRE1_DIV1 0x00000000U
9238#define RCC_CFGR_PPRE1_DIV2 0x00001000U
9239#define RCC_CFGR_PPRE1_DIV4 0x00001400U
9240#define RCC_CFGR_PPRE1_DIV8 0x00001800U
9241#define RCC_CFGR_PPRE1_DIV16 0x00001C00U
9244#define RCC_CFGR_PPRE2_Pos (13U)
9245#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
9246#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
9247#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
9248#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
9249#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
9251#define RCC_CFGR_PPRE2_DIV1 0x00000000U
9252#define RCC_CFGR_PPRE2_DIV2 0x00008000U
9253#define RCC_CFGR_PPRE2_DIV4 0x0000A000U
9254#define RCC_CFGR_PPRE2_DIV8 0x0000C000U
9255#define RCC_CFGR_PPRE2_DIV16 0x0000E000U
9258#define RCC_CFGR_RTCPRE_Pos (16U)
9259#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos)
9260#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
9261#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos)
9262#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos)
9263#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos)
9264#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos)
9265#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
9268#define RCC_CFGR_MCO1_Pos (21U)
9269#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos)
9270#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
9271#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
9272#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
9274#define RCC_CFGR_I2SSRC_Pos (23U)
9275#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos)
9276#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
9277
9278#define RCC_CFGR_MCO1PRE_Pos (24U)
9279#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos)
9280#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
9281#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
9282#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
9283#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
9285#define RCC_CFGR_MCO2PRE_Pos (27U)
9286#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos)
9287#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
9288#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
9289#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
9290#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
9292#define RCC_CFGR_MCO2_Pos (30U)
9293#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos)
9294#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
9295#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
9296#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
9298/******************** Bit definition for RCC_CIR register *******************/
9299#define RCC_CIR_LSIRDYF_Pos (0U)
9300#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
9301#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
9302#define RCC_CIR_LSERDYF_Pos (1U)
9303#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
9304#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
9305#define RCC_CIR_HSIRDYF_Pos (2U)
9306#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
9307#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
9308#define RCC_CIR_HSERDYF_Pos (3U)
9309#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
9310#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
9311#define RCC_CIR_PLLRDYF_Pos (4U)
9312#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
9313#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
9314#define RCC_CIR_PLLI2SRDYF_Pos (5U)
9315#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)
9316#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
9317#define RCC_CIR_PLLSAIRDYF_Pos (6U)
9318#define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos)
9319#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
9320#define RCC_CIR_CSSF_Pos (7U)
9321#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
9322#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
9323#define RCC_CIR_LSIRDYIE_Pos (8U)
9324#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
9325#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
9326#define RCC_CIR_LSERDYIE_Pos (9U)
9327#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
9328#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
9329#define RCC_CIR_HSIRDYIE_Pos (10U)
9330#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
9331#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
9332#define RCC_CIR_HSERDYIE_Pos (11U)
9333#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
9334#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
9335#define RCC_CIR_PLLRDYIE_Pos (12U)
9336#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
9337#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
9338#define RCC_CIR_PLLI2SRDYIE_Pos (13U)
9339#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)
9340#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
9341#define RCC_CIR_PLLSAIRDYIE_Pos (14U)
9342#define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos)
9343#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
9344#define RCC_CIR_LSIRDYC_Pos (16U)
9345#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
9346#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
9347#define RCC_CIR_LSERDYC_Pos (17U)
9348#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
9349#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
9350#define RCC_CIR_HSIRDYC_Pos (18U)
9351#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
9352#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
9353#define RCC_CIR_HSERDYC_Pos (19U)
9354#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
9355#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
9356#define RCC_CIR_PLLRDYC_Pos (20U)
9357#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
9358#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
9359#define RCC_CIR_PLLI2SRDYC_Pos (21U)
9360#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)
9361#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
9362#define RCC_CIR_PLLSAIRDYC_Pos (22U)
9363#define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos)
9364#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
9365#define RCC_CIR_CSSC_Pos (23U)
9366#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
9367#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
9368
9369/******************** Bit definition for RCC_AHB1RSTR register **************/
9370#define RCC_AHB1RSTR_GPIOARST_Pos (0U)
9371#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos)
9372#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
9373#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
9374#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos)
9375#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
9376#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
9377#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos)
9378#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
9379#define RCC_AHB1RSTR_GPIODRST_Pos (3U)
9380#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos)
9381#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
9382#define RCC_AHB1RSTR_GPIOERST_Pos (4U)
9383#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos)
9384#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
9385#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
9386#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos)
9387#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
9388#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
9389#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos)
9390#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
9391#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
9392#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos)
9393#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
9394#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
9395#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos)
9396#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
9397#define RCC_AHB1RSTR_CRCRST_Pos (12U)
9398#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)
9399#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
9400#define RCC_AHB1RSTR_DMA1RST_Pos (21U)
9401#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
9402#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
9403#define RCC_AHB1RSTR_DMA2RST_Pos (22U)
9404#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
9405#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
9406#define RCC_AHB1RSTR_OTGHRST_Pos (29U)
9407#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)
9408#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
9409
9410/******************** Bit definition for RCC_AHB2RSTR register **************/
9411#define RCC_AHB2RSTR_RNGRST_Pos (6U)
9412#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
9413#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
9414#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
9415#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos)
9416#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
9417
9418/******************** Bit definition for RCC_AHB3RSTR register **************/
9419
9420#define RCC_AHB3RSTR_FMCRST_Pos (0U)
9421#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
9422#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
9423#define RCC_AHB3RSTR_QSPIRST_Pos (1U)
9424#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
9425#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
9426
9427/******************** Bit definition for RCC_APB1RSTR register **************/
9428#define RCC_APB1RSTR_TIM2RST_Pos (0U)
9429#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
9430#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
9431#define RCC_APB1RSTR_TIM3RST_Pos (1U)
9432#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
9433#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
9434#define RCC_APB1RSTR_TIM4RST_Pos (2U)
9435#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)
9436#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
9437#define RCC_APB1RSTR_TIM5RST_Pos (3U)
9438#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)
9439#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
9440#define RCC_APB1RSTR_TIM6RST_Pos (4U)
9441#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)
9442#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
9443#define RCC_APB1RSTR_TIM7RST_Pos (5U)
9444#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)
9445#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
9446#define RCC_APB1RSTR_TIM12RST_Pos (6U)
9447#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos)
9448#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
9449#define RCC_APB1RSTR_TIM13RST_Pos (7U)
9450#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos)
9451#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
9452#define RCC_APB1RSTR_TIM14RST_Pos (8U)
9453#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos)
9454#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
9455#define RCC_APB1RSTR_LPTIM1RST_Pos (9U)
9456#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos)
9457#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk
9458#define RCC_APB1RSTR_WWDGRST_Pos (11U)
9459#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
9460#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
9461#define RCC_APB1RSTR_SPI2RST_Pos (14U)
9462#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)
9463#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
9464#define RCC_APB1RSTR_SPI3RST_Pos (15U)
9465#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)
9466#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
9467#define RCC_APB1RSTR_USART2RST_Pos (17U)
9468#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
9469#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
9470#define RCC_APB1RSTR_USART3RST_Pos (18U)
9471#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)
9472#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
9473#define RCC_APB1RSTR_UART4RST_Pos (19U)
9474#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)
9475#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
9476#define RCC_APB1RSTR_UART5RST_Pos (20U)
9477#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)
9478#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
9479#define RCC_APB1RSTR_I2C1RST_Pos (21U)
9480#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
9481#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
9482#define RCC_APB1RSTR_I2C2RST_Pos (22U)
9483#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)
9484#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
9485#define RCC_APB1RSTR_I2C3RST_Pos (23U)
9486#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)
9487#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
9488#define RCC_APB1RSTR_CAN1RST_Pos (25U)
9489#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
9490#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
9491#define RCC_APB1RSTR_PWRRST_Pos (28U)
9492#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
9493#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
9494#define RCC_APB1RSTR_DACRST_Pos (29U)
9495#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)
9496#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
9497#define RCC_APB1RSTR_UART7RST_Pos (30U)
9498#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos)
9499#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
9500#define RCC_APB1RSTR_UART8RST_Pos (31U)
9501#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos)
9502#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
9503
9504/******************** Bit definition for RCC_APB2RSTR register **************/
9505#define RCC_APB2RSTR_TIM1RST_Pos (0U)
9506#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
9507#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
9508#define RCC_APB2RSTR_TIM8RST_Pos (1U)
9509#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
9510#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
9511#define RCC_APB2RSTR_USART1RST_Pos (4U)
9512#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
9513#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
9514#define RCC_APB2RSTR_USART6RST_Pos (5U)
9515#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
9516#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
9517#define RCC_APB2RSTR_SDMMC2RST_Pos (7U)
9518#define RCC_APB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC2RST_Pos)
9519#define RCC_APB2RSTR_SDMMC2RST RCC_APB2RSTR_SDMMC2RST_Msk
9520#define RCC_APB2RSTR_ADCRST_Pos (8U)
9521#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos)
9522#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
9523#define RCC_APB2RSTR_SDMMC1RST_Pos (11U)
9524#define RCC_APB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos)
9525#define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk
9526#define RCC_APB2RSTR_SPI1RST_Pos (12U)
9527#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
9528#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
9529#define RCC_APB2RSTR_SPI4RST_Pos (13U)
9530#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
9531#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
9532#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
9533#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)
9534#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
9535#define RCC_APB2RSTR_TIM9RST_Pos (16U)
9536#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)
9537#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
9538#define RCC_APB2RSTR_TIM10RST_Pos (17U)
9539#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos)
9540#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
9541#define RCC_APB2RSTR_TIM11RST_Pos (18U)
9542#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos)
9543#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
9544#define RCC_APB2RSTR_SPI5RST_Pos (20U)
9545#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
9546#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
9547#define RCC_APB2RSTR_SAI1RST_Pos (22U)
9548#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
9549#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
9550#define RCC_APB2RSTR_SAI2RST_Pos (23U)
9551#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)
9552#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
9553
9554/******************** Bit definition for RCC_AHB1ENR register ***************/
9555#define RCC_AHB1ENR_GPIOAEN_Pos (0U)
9556#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)
9557#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
9558#define RCC_AHB1ENR_GPIOBEN_Pos (1U)
9559#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)
9560#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
9561#define RCC_AHB1ENR_GPIOCEN_Pos (2U)
9562#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)
9563#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
9564#define RCC_AHB1ENR_GPIODEN_Pos (3U)
9565#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)
9566#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
9567#define RCC_AHB1ENR_GPIOEEN_Pos (4U)
9568#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)
9569#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
9570#define RCC_AHB1ENR_GPIOFEN_Pos (5U)
9571#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)
9572#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
9573#define RCC_AHB1ENR_GPIOGEN_Pos (6U)
9574#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)
9575#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
9576#define RCC_AHB1ENR_GPIOHEN_Pos (7U)
9577#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)
9578#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
9579#define RCC_AHB1ENR_GPIOIEN_Pos (8U)
9580#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)
9581#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
9582#define RCC_AHB1ENR_CRCEN_Pos (12U)
9583#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos)
9584#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
9585#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
9586#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos)
9587#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
9588#define RCC_AHB1ENR_DTCMRAMEN_Pos (20U)
9589#define RCC_AHB1ENR_DTCMRAMEN_Msk (0x1UL << RCC_AHB1ENR_DTCMRAMEN_Pos)
9590#define RCC_AHB1ENR_DTCMRAMEN RCC_AHB1ENR_DTCMRAMEN_Msk
9591#define RCC_AHB1ENR_DMA1EN_Pos (21U)
9592#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
9593#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
9594#define RCC_AHB1ENR_DMA2EN_Pos (22U)
9595#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
9596#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
9597#define RCC_AHB1ENR_OTGHSEN_Pos (29U)
9598#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)
9599#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
9600#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
9601#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos)
9602#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
9603
9604/******************** Bit definition for RCC_AHB2ENR register ***************/
9605#define RCC_AHB2ENR_RNGEN_Pos (6U)
9606#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
9607#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
9608#define RCC_AHB2ENR_OTGFSEN_Pos (7U)
9609#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)
9610#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
9611
9612/******************** Bit definition for RCC_AHB3ENR register ***************/
9613#define RCC_AHB3ENR_FMCEN_Pos (0U)
9614#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
9615#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
9616#define RCC_AHB3ENR_QSPIEN_Pos (1U)
9617#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
9618#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
9619
9620/******************** Bit definition for RCC_APB1ENR register ***************/
9621#define RCC_APB1ENR_TIM2EN_Pos (0U)
9622#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
9623#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
9624#define RCC_APB1ENR_TIM3EN_Pos (1U)
9625#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
9626#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
9627#define RCC_APB1ENR_TIM4EN_Pos (2U)
9628#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)
9629#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
9630#define RCC_APB1ENR_TIM5EN_Pos (3U)
9631#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)
9632#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
9633#define RCC_APB1ENR_TIM6EN_Pos (4U)
9634#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)
9635#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
9636#define RCC_APB1ENR_TIM7EN_Pos (5U)
9637#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)
9638#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
9639#define RCC_APB1ENR_TIM12EN_Pos (6U)
9640#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos)
9641#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
9642#define RCC_APB1ENR_TIM13EN_Pos (7U)
9643#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos)
9644#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
9645#define RCC_APB1ENR_TIM14EN_Pos (8U)
9646#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos)
9647#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
9648#define RCC_APB1ENR_LPTIM1EN_Pos (9U)
9649#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos)
9650#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
9651#define RCC_APB1ENR_RTCEN_Pos (10U)
9652#define RCC_APB1ENR_RTCEN_Msk (0x1UL << RCC_APB1ENR_RTCEN_Pos)
9653#define RCC_APB1ENR_RTCEN RCC_APB1ENR_RTCEN_Msk
9654#define RCC_APB1ENR_WWDGEN_Pos (11U)
9655#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
9656#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
9657#define RCC_APB1ENR_SPI2EN_Pos (14U)
9658#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)
9659#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
9660#define RCC_APB1ENR_SPI3EN_Pos (15U)
9661#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)
9662#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
9663#define RCC_APB1ENR_USART2EN_Pos (17U)
9664#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
9665#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
9666#define RCC_APB1ENR_USART3EN_Pos (18U)
9667#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)
9668#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
9669#define RCC_APB1ENR_UART4EN_Pos (19U)
9670#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)
9671#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
9672#define RCC_APB1ENR_UART5EN_Pos (20U)
9673#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)
9674#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
9675#define RCC_APB1ENR_I2C1EN_Pos (21U)
9676#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
9677#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
9678#define RCC_APB1ENR_I2C2EN_Pos (22U)
9679#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)
9680#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
9681#define RCC_APB1ENR_I2C3EN_Pos (23U)
9682#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos)
9683#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
9684#define RCC_APB1ENR_CAN1EN_Pos (25U)
9685#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
9686#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
9687#define RCC_APB1ENR_PWREN_Pos (28U)
9688#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
9689#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
9690#define RCC_APB1ENR_DACEN_Pos (29U)
9691#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)
9692#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
9693#define RCC_APB1ENR_UART7EN_Pos (30U)
9694#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos)
9695#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
9696#define RCC_APB1ENR_UART8EN_Pos (31U)
9697#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos)
9698#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
9699
9700/******************** Bit definition for RCC_APB2ENR register ***************/
9701#define RCC_APB2ENR_TIM1EN_Pos (0U)
9702#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
9703#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
9704#define RCC_APB2ENR_TIM8EN_Pos (1U)
9705#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
9706#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
9707#define RCC_APB2ENR_USART1EN_Pos (4U)
9708#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
9709#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
9710#define RCC_APB2ENR_USART6EN_Pos (5U)
9711#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
9712#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
9713#define RCC_APB2ENR_SDMMC2EN_Pos (7U)
9714#define RCC_APB2ENR_SDMMC2EN_Msk (0x1UL << RCC_APB2ENR_SDMMC2EN_Pos)
9715#define RCC_APB2ENR_SDMMC2EN RCC_APB2ENR_SDMMC2EN_Msk
9716#define RCC_APB2ENR_ADC1EN_Pos (8U)
9717#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
9718#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
9719#define RCC_APB2ENR_ADC2EN_Pos (9U)
9720#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
9721#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
9722#define RCC_APB2ENR_ADC3EN_Pos (10U)
9723#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos)
9724#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
9725#define RCC_APB2ENR_SDMMC1EN_Pos (11U)
9726#define RCC_APB2ENR_SDMMC1EN_Msk (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos)
9727#define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk
9728#define RCC_APB2ENR_SPI1EN_Pos (12U)
9729#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
9730#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
9731#define RCC_APB2ENR_SPI4EN_Pos (13U)
9732#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
9733#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
9734#define RCC_APB2ENR_SYSCFGEN_Pos (14U)
9735#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)
9736#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
9737#define RCC_APB2ENR_TIM9EN_Pos (16U)
9738#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos)
9739#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
9740#define RCC_APB2ENR_TIM10EN_Pos (17U)
9741#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos)
9742#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
9743#define RCC_APB2ENR_TIM11EN_Pos (18U)
9744#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos)
9745#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
9746#define RCC_APB2ENR_SPI5EN_Pos (20U)
9747#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
9748#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
9749#define RCC_APB2ENR_SAI1EN_Pos (22U)
9750#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
9751#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
9752#define RCC_APB2ENR_SAI2EN_Pos (23U)
9753#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos)
9754#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
9755
9756/******************** Bit definition for RCC_AHB1LPENR register *************/
9757#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
9758#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos)
9759#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
9760#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
9761#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos)
9762#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
9763#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
9764#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos)
9765#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
9766#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
9767#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos)
9768#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
9769#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
9770#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos)
9771#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
9772#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
9773#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos)
9774#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
9775#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
9776#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos)
9777#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
9778#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
9779#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos)
9780#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
9781#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
9782#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos)
9783#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
9784#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
9785#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos)
9786#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
9787#define RCC_AHB1LPENR_AXILPEN_Pos (13U)
9788#define RCC_AHB1LPENR_AXILPEN_Msk (0x1UL << RCC_AHB1LPENR_AXILPEN_Pos)
9789#define RCC_AHB1LPENR_AXILPEN RCC_AHB1LPENR_AXILPEN_Msk
9790#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
9791#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos)
9792#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
9793#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
9794#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos)
9795#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
9796#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
9797#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos)
9798#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
9799#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
9800#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos)
9801#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
9802#define RCC_AHB1LPENR_DTCMLPEN_Pos (20U)
9803#define RCC_AHB1LPENR_DTCMLPEN_Msk (0x1UL << RCC_AHB1LPENR_DTCMLPEN_Pos)
9804#define RCC_AHB1LPENR_DTCMLPEN RCC_AHB1LPENR_DTCMLPEN_Msk
9805#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
9806#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
9807#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
9808#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
9809#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
9810#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
9811#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
9812#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos)
9813#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
9814#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
9815#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos)
9816#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
9817
9818/******************** Bit definition for RCC_AHB2LPENR register *************/
9819#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
9820#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
9821#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
9822#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
9823#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos)
9824#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
9825
9826/******************** Bit definition for RCC_AHB3LPENR register *************/
9827#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
9828#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
9829#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
9830#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
9831#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
9832#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
9833/******************** Bit definition for RCC_APB1LPENR register *************/
9834#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
9835#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos)
9836#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
9837#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
9838#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos)
9839#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
9840#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
9841#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos)
9842#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
9843#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
9844#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos)
9845#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
9846#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
9847#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos)
9848#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
9849#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
9850#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos)
9851#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
9852#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
9853#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos)
9854#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
9855#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
9856#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos)
9857#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
9858#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
9859#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos)
9860#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
9861#define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)
9862#define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos)
9863#define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk
9864#define RCC_APB1LPENR_RTCLPEN_Pos (10U)
9865#define RCC_APB1LPENR_RTCLPEN_Msk (0x1UL << RCC_APB1LPENR_RTCLPEN_Pos)
9866#define RCC_APB1LPENR_RTCLPEN RCC_APB1LPENR_RTCLPEN_Msk
9867#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
9868#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos)
9869#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
9870#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
9871#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos)
9872#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
9873#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
9874#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos)
9875#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
9876#define RCC_APB1LPENR_USART2LPEN_Pos (17U)
9877#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos)
9878#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
9879#define RCC_APB1LPENR_USART3LPEN_Pos (18U)
9880#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos)
9881#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
9882#define RCC_APB1LPENR_UART4LPEN_Pos (19U)
9883#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos)
9884#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
9885#define RCC_APB1LPENR_UART5LPEN_Pos (20U)
9886#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos)
9887#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
9888#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
9889#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos)
9890#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
9891#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
9892#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos)
9893#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
9894#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
9895#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos)
9896#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
9897#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
9898#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos)
9899#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
9900#define RCC_APB1LPENR_PWRLPEN_Pos (28U)
9901#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos)
9902#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
9903#define RCC_APB1LPENR_DACLPEN_Pos (29U)
9904#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos)
9905#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
9906#define RCC_APB1LPENR_UART7LPEN_Pos (30U)
9907#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos)
9908#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
9909#define RCC_APB1LPENR_UART8LPEN_Pos (31U)
9910#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos)
9911#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
9912
9913/******************** Bit definition for RCC_APB2LPENR register *************/
9914#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
9915#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
9916#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
9917#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
9918#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
9919#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
9920#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
9921#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
9922#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
9923#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
9924#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
9925#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
9926#define RCC_APB2LPENR_SDMMC2LPEN_Pos (7U)
9927#define RCC_APB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC2LPEN_Pos)
9928#define RCC_APB2LPENR_SDMMC2LPEN RCC_APB2LPENR_SDMMC2LPEN_Msk
9929#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
9930#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos)
9931#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
9932#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
9933#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos)
9934#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
9935#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
9936#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos)
9937#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
9938#define RCC_APB2LPENR_SDMMC1LPEN_Pos (11U)
9939#define RCC_APB2LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC1LPEN_Pos)
9940#define RCC_APB2LPENR_SDMMC1LPEN RCC_APB2LPENR_SDMMC1LPEN_Msk
9941#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
9942#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
9943#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
9944#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
9945#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
9946#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
9947#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
9948#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos)
9949#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
9950#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
9951#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos)
9952#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
9953#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
9954#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos)
9955#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
9956#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
9957#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos)
9958#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
9959#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
9960#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
9961#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
9962#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
9963#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
9964#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
9965#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
9966#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos)
9967#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
9968
9969/******************** Bit definition for RCC_BDCR register ******************/
9970#define RCC_BDCR_LSEON_Pos (0U)
9971#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
9972#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
9973#define RCC_BDCR_LSERDY_Pos (1U)
9974#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
9975#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
9976#define RCC_BDCR_LSEBYP_Pos (2U)
9977#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
9978#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
9979#define RCC_BDCR_LSEDRV_Pos (3U)
9980#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
9981#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
9982#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
9983#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
9984#define RCC_BDCR_RTCSEL_Pos (8U)
9985#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
9986#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
9987#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
9988#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
9989#define RCC_BDCR_RTCEN_Pos (15U)
9990#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
9991#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
9992#define RCC_BDCR_BDRST_Pos (16U)
9993#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
9994#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
9995
9996/******************** Bit definition for RCC_CSR register *******************/
9997#define RCC_CSR_LSION_Pos (0U)
9998#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
9999#define RCC_CSR_LSION RCC_CSR_LSION_Msk
10000#define RCC_CSR_LSIRDY_Pos (1U)
10001#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
10002#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
10003#define RCC_CSR_RMVF_Pos (24U)
10004#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
10005#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
10006#define RCC_CSR_BORRSTF_Pos (25U)
10007#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos)
10008#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
10009#define RCC_CSR_PINRSTF_Pos (26U)
10010#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
10011#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
10012#define RCC_CSR_PORRSTF_Pos (27U)
10013#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
10014#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
10015#define RCC_CSR_SFTRSTF_Pos (28U)
10016#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
10017#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
10018#define RCC_CSR_IWDGRSTF_Pos (29U)
10019#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
10020#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
10021#define RCC_CSR_WWDGRSTF_Pos (30U)
10022#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
10023#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
10024#define RCC_CSR_LPWRRSTF_Pos (31U)
10025#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
10026#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
10027
10028/******************** Bit definition for RCC_SSCGR register *****************/
10029#define RCC_SSCGR_MODPER_Pos (0U)
10030#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos)
10031#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
10032#define RCC_SSCGR_INCSTEP_Pos (13U)
10033#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)
10034#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
10035#define RCC_SSCGR_SPREADSEL_Pos (30U)
10036#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos)
10037#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
10038#define RCC_SSCGR_SSCGEN_Pos (31U)
10039#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos)
10040#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
10041
10042/******************** Bit definition for RCC_PLLI2SCFGR register ************/
10043#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
10044#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10045#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
10046#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10047#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10048#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10049#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10050#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10051#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10052#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10053#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10054#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos)
10055#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
10056#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10057#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
10058#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10059#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10060#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10061#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos)
10062#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
10063#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10064#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
10065#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10066#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10067#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos)
10069/******************** Bit definition for RCC_PLLSAICFGR register ************/
10070#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
10071#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10072#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
10073#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10074#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10075#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10076#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10077#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10078#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10079#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10080#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10081#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos)
10082#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
10083#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
10084#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
10085#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
10086#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos)
10087#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
10088#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
10089#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
10090#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
10091#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
10092#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
10093#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos)
10095/******************** Bit definition for RCC_DCKCFGR1 register ***************/
10096#define RCC_DCKCFGR1_PLLI2SDIVQ_Pos (0U)
10097#define RCC_DCKCFGR1_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
10098#define RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ_Msk
10099#define RCC_DCKCFGR1_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
10100#define RCC_DCKCFGR1_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
10101#define RCC_DCKCFGR1_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
10102#define RCC_DCKCFGR1_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
10103#define RCC_DCKCFGR1_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos)
10105#define RCC_DCKCFGR1_PLLSAIDIVQ_Pos (8U)
10106#define RCC_DCKCFGR1_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
10107#define RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ_Msk
10108#define RCC_DCKCFGR1_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
10109#define RCC_DCKCFGR1_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
10110#define RCC_DCKCFGR1_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
10111#define RCC_DCKCFGR1_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
10112#define RCC_DCKCFGR1_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos)
10115#define RCC_DCKCFGR1_SAI1SEL_Pos (20U)
10116#define RCC_DCKCFGR1_SAI1SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI1SEL_Pos)
10117#define RCC_DCKCFGR1_SAI1SEL RCC_DCKCFGR1_SAI1SEL_Msk
10118#define RCC_DCKCFGR1_SAI1SEL_0 (0x1UL << RCC_DCKCFGR1_SAI1SEL_Pos)
10119#define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos)
10121#define RCC_DCKCFGR1_SAI2SEL_Pos (22U)
10122#define RCC_DCKCFGR1_SAI2SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI2SEL_Pos)
10123#define RCC_DCKCFGR1_SAI2SEL RCC_DCKCFGR1_SAI2SEL_Msk
10124#define RCC_DCKCFGR1_SAI2SEL_0 (0x1UL << RCC_DCKCFGR1_SAI2SEL_Pos)
10125#define RCC_DCKCFGR1_SAI2SEL_1 (0x2UL << RCC_DCKCFGR1_SAI2SEL_Pos)
10127#define RCC_DCKCFGR1_TIMPRE_Pos (24U)
10128#define RCC_DCKCFGR1_TIMPRE_Msk (0x1UL << RCC_DCKCFGR1_TIMPRE_Pos)
10129#define RCC_DCKCFGR1_TIMPRE RCC_DCKCFGR1_TIMPRE_Msk
10130
10131/******************** Bit definition for RCC_DCKCFGR2 register ***************/
10132#define RCC_DCKCFGR2_USART1SEL_Pos (0U)
10133#define RCC_DCKCFGR2_USART1SEL_Msk (0x3UL << RCC_DCKCFGR2_USART1SEL_Pos)
10134#define RCC_DCKCFGR2_USART1SEL RCC_DCKCFGR2_USART1SEL_Msk
10135#define RCC_DCKCFGR2_USART1SEL_0 (0x1UL << RCC_DCKCFGR2_USART1SEL_Pos)
10136#define RCC_DCKCFGR2_USART1SEL_1 (0x2UL << RCC_DCKCFGR2_USART1SEL_Pos)
10137#define RCC_DCKCFGR2_USART2SEL_Pos (2U)
10138#define RCC_DCKCFGR2_USART2SEL_Msk (0x3UL << RCC_DCKCFGR2_USART2SEL_Pos)
10139#define RCC_DCKCFGR2_USART2SEL RCC_DCKCFGR2_USART2SEL_Msk
10140#define RCC_DCKCFGR2_USART2SEL_0 (0x1UL << RCC_DCKCFGR2_USART2SEL_Pos)
10141#define RCC_DCKCFGR2_USART2SEL_1 (0x2UL << RCC_DCKCFGR2_USART2SEL_Pos)
10142#define RCC_DCKCFGR2_USART3SEL_Pos (4U)
10143#define RCC_DCKCFGR2_USART3SEL_Msk (0x3UL << RCC_DCKCFGR2_USART3SEL_Pos)
10144#define RCC_DCKCFGR2_USART3SEL RCC_DCKCFGR2_USART3SEL_Msk
10145#define RCC_DCKCFGR2_USART3SEL_0 (0x1UL << RCC_DCKCFGR2_USART3SEL_Pos)
10146#define RCC_DCKCFGR2_USART3SEL_1 (0x2UL << RCC_DCKCFGR2_USART3SEL_Pos)
10147#define RCC_DCKCFGR2_UART4SEL_Pos (6U)
10148#define RCC_DCKCFGR2_UART4SEL_Msk (0x3UL << RCC_DCKCFGR2_UART4SEL_Pos)
10149#define RCC_DCKCFGR2_UART4SEL RCC_DCKCFGR2_UART4SEL_Msk
10150#define RCC_DCKCFGR2_UART4SEL_0 (0x1UL << RCC_DCKCFGR2_UART4SEL_Pos)
10151#define RCC_DCKCFGR2_UART4SEL_1 (0x2UL << RCC_DCKCFGR2_UART4SEL_Pos)
10152#define RCC_DCKCFGR2_UART5SEL_Pos (8U)
10153#define RCC_DCKCFGR2_UART5SEL_Msk (0x3UL << RCC_DCKCFGR2_UART5SEL_Pos)
10154#define RCC_DCKCFGR2_UART5SEL RCC_DCKCFGR2_UART5SEL_Msk
10155#define RCC_DCKCFGR2_UART5SEL_0 (0x1UL << RCC_DCKCFGR2_UART5SEL_Pos)
10156#define RCC_DCKCFGR2_UART5SEL_1 (0x2UL << RCC_DCKCFGR2_UART5SEL_Pos)
10157#define RCC_DCKCFGR2_USART6SEL_Pos (10U)
10158#define RCC_DCKCFGR2_USART6SEL_Msk (0x3UL << RCC_DCKCFGR2_USART6SEL_Pos)
10159#define RCC_DCKCFGR2_USART6SEL RCC_DCKCFGR2_USART6SEL_Msk
10160#define RCC_DCKCFGR2_USART6SEL_0 (0x1UL << RCC_DCKCFGR2_USART6SEL_Pos)
10161#define RCC_DCKCFGR2_USART6SEL_1 (0x2UL << RCC_DCKCFGR2_USART6SEL_Pos)
10162#define RCC_DCKCFGR2_UART7SEL_Pos (12U)
10163#define RCC_DCKCFGR2_UART7SEL_Msk (0x3UL << RCC_DCKCFGR2_UART7SEL_Pos)
10164#define RCC_DCKCFGR2_UART7SEL RCC_DCKCFGR2_UART7SEL_Msk
10165#define RCC_DCKCFGR2_UART7SEL_0 (0x1UL << RCC_DCKCFGR2_UART7SEL_Pos)
10166#define RCC_DCKCFGR2_UART7SEL_1 (0x2UL << RCC_DCKCFGR2_UART7SEL_Pos)
10167#define RCC_DCKCFGR2_UART8SEL_Pos (14U)
10168#define RCC_DCKCFGR2_UART8SEL_Msk (0x3UL << RCC_DCKCFGR2_UART8SEL_Pos)
10169#define RCC_DCKCFGR2_UART8SEL RCC_DCKCFGR2_UART8SEL_Msk
10170#define RCC_DCKCFGR2_UART8SEL_0 (0x1UL << RCC_DCKCFGR2_UART8SEL_Pos)
10171#define RCC_DCKCFGR2_UART8SEL_1 (0x2UL << RCC_DCKCFGR2_UART8SEL_Pos)
10172#define RCC_DCKCFGR2_I2C1SEL_Pos (16U)
10173#define RCC_DCKCFGR2_I2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C1SEL_Pos)
10174#define RCC_DCKCFGR2_I2C1SEL RCC_DCKCFGR2_I2C1SEL_Msk
10175#define RCC_DCKCFGR2_I2C1SEL_0 (0x1UL << RCC_DCKCFGR2_I2C1SEL_Pos)
10176#define RCC_DCKCFGR2_I2C1SEL_1 (0x2UL << RCC_DCKCFGR2_I2C1SEL_Pos)
10177#define RCC_DCKCFGR2_I2C2SEL_Pos (18U)
10178#define RCC_DCKCFGR2_I2C2SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C2SEL_Pos)
10179#define RCC_DCKCFGR2_I2C2SEL RCC_DCKCFGR2_I2C2SEL_Msk
10180#define RCC_DCKCFGR2_I2C2SEL_0 (0x1UL << RCC_DCKCFGR2_I2C2SEL_Pos)
10181#define RCC_DCKCFGR2_I2C2SEL_1 (0x2UL << RCC_DCKCFGR2_I2C2SEL_Pos)
10182#define RCC_DCKCFGR2_I2C3SEL_Pos (20U)
10183#define RCC_DCKCFGR2_I2C3SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C3SEL_Pos)
10184#define RCC_DCKCFGR2_I2C3SEL RCC_DCKCFGR2_I2C3SEL_Msk
10185#define RCC_DCKCFGR2_I2C3SEL_0 (0x1UL << RCC_DCKCFGR2_I2C3SEL_Pos)
10186#define RCC_DCKCFGR2_I2C3SEL_1 (0x2UL << RCC_DCKCFGR2_I2C3SEL_Pos)
10187#define RCC_DCKCFGR2_LPTIM1SEL_Pos (24U)
10188#define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
10189#define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk
10190#define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
10191#define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos)
10192#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)
10193#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos)
10194#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk
10195#define RCC_DCKCFGR2_SDMMC1SEL_Pos (28U)
10196#define RCC_DCKCFGR2_SDMMC1SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC1SEL_Pos)
10197#define RCC_DCKCFGR2_SDMMC1SEL RCC_DCKCFGR2_SDMMC1SEL_Msk
10198#define RCC_DCKCFGR2_SDMMC2SEL_Pos (29U)
10199#define RCC_DCKCFGR2_SDMMC2SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC2SEL_Pos)
10200#define RCC_DCKCFGR2_SDMMC2SEL RCC_DCKCFGR2_SDMMC2SEL_Msk
10201
10202/******************************************************************************/
10203/* */
10204/* RNG */
10205/* */
10206/******************************************************************************/
10207/******************** Bits definition for RNG_CR register *******************/
10208#define RNG_CR_RNGEN_Pos (2U)
10209#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
10210#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10211#define RNG_CR_IE_Pos (3U)
10212#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
10213#define RNG_CR_IE RNG_CR_IE_Msk
10214
10215/******************** Bits definition for RNG_SR register *******************/
10216#define RNG_SR_DRDY_Pos (0U)
10217#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
10218#define RNG_SR_DRDY RNG_SR_DRDY_Msk
10219#define RNG_SR_CECS_Pos (1U)
10220#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
10221#define RNG_SR_CECS RNG_SR_CECS_Msk
10222#define RNG_SR_SECS_Pos (2U)
10223#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
10224#define RNG_SR_SECS RNG_SR_SECS_Msk
10225#define RNG_SR_CEIS_Pos (5U)
10226#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
10227#define RNG_SR_CEIS RNG_SR_CEIS_Msk
10228#define RNG_SR_SEIS_Pos (6U)
10229#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
10230#define RNG_SR_SEIS RNG_SR_SEIS_Msk
10231
10232/******************************************************************************/
10233/* */
10234/* Real-Time Clock (RTC) */
10235/* */
10236/******************************************************************************/
10237/******************** Bits definition for RTC_TR register *******************/
10238#define RTC_TR_PM_Pos (22U)
10239#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
10240#define RTC_TR_PM RTC_TR_PM_Msk
10241#define RTC_TR_HT_Pos (20U)
10242#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
10243#define RTC_TR_HT RTC_TR_HT_Msk
10244#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
10245#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
10246#define RTC_TR_HU_Pos (16U)
10247#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
10248#define RTC_TR_HU RTC_TR_HU_Msk
10249#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
10250#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
10251#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
10252#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
10253#define RTC_TR_MNT_Pos (12U)
10254#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
10255#define RTC_TR_MNT RTC_TR_MNT_Msk
10256#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
10257#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
10258#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
10259#define RTC_TR_MNU_Pos (8U)
10260#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
10261#define RTC_TR_MNU RTC_TR_MNU_Msk
10262#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
10263#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
10264#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
10265#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
10266#define RTC_TR_ST_Pos (4U)
10267#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
10268#define RTC_TR_ST RTC_TR_ST_Msk
10269#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
10270#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
10271#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
10272#define RTC_TR_SU_Pos (0U)
10273#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
10274#define RTC_TR_SU RTC_TR_SU_Msk
10275#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
10276#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
10277#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
10278#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
10280/******************** Bits definition for RTC_DR register *******************/
10281#define RTC_DR_YT_Pos (20U)
10282#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
10283#define RTC_DR_YT RTC_DR_YT_Msk
10284#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
10285#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
10286#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
10287#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
10288#define RTC_DR_YU_Pos (16U)
10289#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
10290#define RTC_DR_YU RTC_DR_YU_Msk
10291#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
10292#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
10293#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
10294#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
10295#define RTC_DR_WDU_Pos (13U)
10296#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
10297#define RTC_DR_WDU RTC_DR_WDU_Msk
10298#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
10299#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
10300#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
10301#define RTC_DR_MT_Pos (12U)
10302#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
10303#define RTC_DR_MT RTC_DR_MT_Msk
10304#define RTC_DR_MU_Pos (8U)
10305#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
10306#define RTC_DR_MU RTC_DR_MU_Msk
10307#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
10308#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
10309#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
10310#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
10311#define RTC_DR_DT_Pos (4U)
10312#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
10313#define RTC_DR_DT RTC_DR_DT_Msk
10314#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
10315#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
10316#define RTC_DR_DU_Pos (0U)
10317#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
10318#define RTC_DR_DU RTC_DR_DU_Msk
10319#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
10320#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
10321#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
10322#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
10324/******************** Bits definition for RTC_CR register *******************/
10325#define RTC_CR_ITSE_Pos (24U)
10326#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
10327#define RTC_CR_ITSE RTC_CR_ITSE_Msk
10328#define RTC_CR_COE_Pos (23U)
10329#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
10330#define RTC_CR_COE RTC_CR_COE_Msk
10331#define RTC_CR_OSEL_Pos (21U)
10332#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
10333#define RTC_CR_OSEL RTC_CR_OSEL_Msk
10334#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
10335#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
10336#define RTC_CR_POL_Pos (20U)
10337#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
10338#define RTC_CR_POL RTC_CR_POL_Msk
10339#define RTC_CR_COSEL_Pos (19U)
10340#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
10341#define RTC_CR_COSEL RTC_CR_COSEL_Msk
10342#define RTC_CR_BKP_Pos (18U)
10343#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
10344#define RTC_CR_BKP RTC_CR_BKP_Msk
10345#define RTC_CR_SUB1H_Pos (17U)
10346#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
10347#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
10348#define RTC_CR_ADD1H_Pos (16U)
10349#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
10350#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
10351#define RTC_CR_TSIE_Pos (15U)
10352#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
10353#define RTC_CR_TSIE RTC_CR_TSIE_Msk
10354#define RTC_CR_WUTIE_Pos (14U)
10355#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
10356#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
10357#define RTC_CR_ALRBIE_Pos (13U)
10358#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
10359#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
10360#define RTC_CR_ALRAIE_Pos (12U)
10361#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
10362#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
10363#define RTC_CR_TSE_Pos (11U)
10364#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
10365#define RTC_CR_TSE RTC_CR_TSE_Msk
10366#define RTC_CR_WUTE_Pos (10U)
10367#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
10368#define RTC_CR_WUTE RTC_CR_WUTE_Msk
10369#define RTC_CR_ALRBE_Pos (9U)
10370#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
10371#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
10372#define RTC_CR_ALRAE_Pos (8U)
10373#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
10374#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
10375#define RTC_CR_FMT_Pos (6U)
10376#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
10377#define RTC_CR_FMT RTC_CR_FMT_Msk
10378#define RTC_CR_BYPSHAD_Pos (5U)
10379#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
10380#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
10381#define RTC_CR_REFCKON_Pos (4U)
10382#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
10383#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
10384#define RTC_CR_TSEDGE_Pos (3U)
10385#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
10386#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
10387#define RTC_CR_WUCKSEL_Pos (0U)
10388#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
10389#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
10390#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
10391#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
10392#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
10394/* Legacy define */
10395#define RTC_CR_BCK RTC_CR_BKP
10396
10397/******************** Bits definition for RTC_ISR register ******************/
10398#define RTC_ISR_ITSF_Pos (17U)
10399#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
10400#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
10401#define RTC_ISR_RECALPF_Pos (16U)
10402#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
10403#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
10404#define RTC_ISR_TAMP3F_Pos (15U)
10405#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
10406#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
10407#define RTC_ISR_TAMP2F_Pos (14U)
10408#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
10409#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
10410#define RTC_ISR_TAMP1F_Pos (13U)
10411#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
10412#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
10413#define RTC_ISR_TSOVF_Pos (12U)
10414#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
10415#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
10416#define RTC_ISR_TSF_Pos (11U)
10417#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
10418#define RTC_ISR_TSF RTC_ISR_TSF_Msk
10419#define RTC_ISR_WUTF_Pos (10U)
10420#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
10421#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
10422#define RTC_ISR_ALRBF_Pos (9U)
10423#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
10424#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
10425#define RTC_ISR_ALRAF_Pos (8U)
10426#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
10427#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
10428#define RTC_ISR_INIT_Pos (7U)
10429#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
10430#define RTC_ISR_INIT RTC_ISR_INIT_Msk
10431#define RTC_ISR_INITF_Pos (6U)
10432#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
10433#define RTC_ISR_INITF RTC_ISR_INITF_Msk
10434#define RTC_ISR_RSF_Pos (5U)
10435#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
10436#define RTC_ISR_RSF RTC_ISR_RSF_Msk
10437#define RTC_ISR_INITS_Pos (4U)
10438#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
10439#define RTC_ISR_INITS RTC_ISR_INITS_Msk
10440#define RTC_ISR_SHPF_Pos (3U)
10441#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
10442#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
10443#define RTC_ISR_WUTWF_Pos (2U)
10444#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
10445#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
10446#define RTC_ISR_ALRBWF_Pos (1U)
10447#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
10448#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
10449#define RTC_ISR_ALRAWF_Pos (0U)
10450#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
10451#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
10452
10453/******************** Bits definition for RTC_PRER register *****************/
10454#define RTC_PRER_PREDIV_A_Pos (16U)
10455#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
10456#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
10457#define RTC_PRER_PREDIV_S_Pos (0U)
10458#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
10459#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
10460
10461/******************** Bits definition for RTC_WUTR register *****************/
10462#define RTC_WUTR_WUT_Pos (0U)
10463#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
10464#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
10465
10466/******************** Bits definition for RTC_ALRMAR register ***************/
10467#define RTC_ALRMAR_MSK4_Pos (31U)
10468#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
10469#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
10470#define RTC_ALRMAR_WDSEL_Pos (30U)
10471#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
10472#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
10473#define RTC_ALRMAR_DT_Pos (28U)
10474#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
10475#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
10476#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
10477#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
10478#define RTC_ALRMAR_DU_Pos (24U)
10479#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
10480#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
10481#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
10482#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
10483#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
10484#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
10485#define RTC_ALRMAR_MSK3_Pos (23U)
10486#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
10487#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
10488#define RTC_ALRMAR_PM_Pos (22U)
10489#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
10490#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
10491#define RTC_ALRMAR_HT_Pos (20U)
10492#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
10493#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
10494#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
10495#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
10496#define RTC_ALRMAR_HU_Pos (16U)
10497#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
10498#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
10499#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
10500#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
10501#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
10502#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
10503#define RTC_ALRMAR_MSK2_Pos (15U)
10504#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
10505#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
10506#define RTC_ALRMAR_MNT_Pos (12U)
10507#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
10508#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
10509#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
10510#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
10511#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
10512#define RTC_ALRMAR_MNU_Pos (8U)
10513#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
10514#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
10515#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
10516#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
10517#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
10518#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
10519#define RTC_ALRMAR_MSK1_Pos (7U)
10520#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
10521#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
10522#define RTC_ALRMAR_ST_Pos (4U)
10523#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
10524#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
10525#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
10526#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
10527#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
10528#define RTC_ALRMAR_SU_Pos (0U)
10529#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
10530#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
10531#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
10532#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
10533#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
10534#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
10536/******************** Bits definition for RTC_ALRMBR register ***************/
10537#define RTC_ALRMBR_MSK4_Pos (31U)
10538#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
10539#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
10540#define RTC_ALRMBR_WDSEL_Pos (30U)
10541#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
10542#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
10543#define RTC_ALRMBR_DT_Pos (28U)
10544#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
10545#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
10546#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
10547#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
10548#define RTC_ALRMBR_DU_Pos (24U)
10549#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
10550#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
10551#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
10552#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
10553#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
10554#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
10555#define RTC_ALRMBR_MSK3_Pos (23U)
10556#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
10557#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
10558#define RTC_ALRMBR_PM_Pos (22U)
10559#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
10560#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
10561#define RTC_ALRMBR_HT_Pos (20U)
10562#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
10563#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
10564#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
10565#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
10566#define RTC_ALRMBR_HU_Pos (16U)
10567#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
10568#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
10569#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
10570#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
10571#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
10572#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
10573#define RTC_ALRMBR_MSK2_Pos (15U)
10574#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
10575#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
10576#define RTC_ALRMBR_MNT_Pos (12U)
10577#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
10578#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
10579#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
10580#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
10581#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
10582#define RTC_ALRMBR_MNU_Pos (8U)
10583#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
10584#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
10585#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
10586#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
10587#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
10588#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
10589#define RTC_ALRMBR_MSK1_Pos (7U)
10590#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
10591#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
10592#define RTC_ALRMBR_ST_Pos (4U)
10593#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
10594#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
10595#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
10596#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
10597#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
10598#define RTC_ALRMBR_SU_Pos (0U)
10599#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
10600#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
10601#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
10602#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
10603#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
10604#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
10606/******************** Bits definition for RTC_WPR register ******************/
10607#define RTC_WPR_KEY_Pos (0U)
10608#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
10609#define RTC_WPR_KEY RTC_WPR_KEY_Msk
10610
10611/******************** Bits definition for RTC_SSR register ******************/
10612#define RTC_SSR_SS_Pos (0U)
10613#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
10614#define RTC_SSR_SS RTC_SSR_SS_Msk
10615
10616/******************** Bits definition for RTC_SHIFTR register ***************/
10617#define RTC_SHIFTR_SUBFS_Pos (0U)
10618#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
10619#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
10620#define RTC_SHIFTR_ADD1S_Pos (31U)
10621#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
10622#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
10623
10624/******************** Bits definition for RTC_TSTR register *****************/
10625#define RTC_TSTR_PM_Pos (22U)
10626#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
10627#define RTC_TSTR_PM RTC_TSTR_PM_Msk
10628#define RTC_TSTR_HT_Pos (20U)
10629#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
10630#define RTC_TSTR_HT RTC_TSTR_HT_Msk
10631#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
10632#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
10633#define RTC_TSTR_HU_Pos (16U)
10634#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
10635#define RTC_TSTR_HU RTC_TSTR_HU_Msk
10636#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
10637#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
10638#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
10639#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
10640#define RTC_TSTR_MNT_Pos (12U)
10641#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
10642#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
10643#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
10644#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
10645#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
10646#define RTC_TSTR_MNU_Pos (8U)
10647#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
10648#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
10649#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
10650#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
10651#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
10652#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
10653#define RTC_TSTR_ST_Pos (4U)
10654#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
10655#define RTC_TSTR_ST RTC_TSTR_ST_Msk
10656#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
10657#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
10658#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
10659#define RTC_TSTR_SU_Pos (0U)
10660#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
10661#define RTC_TSTR_SU RTC_TSTR_SU_Msk
10662#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
10663#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
10664#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
10665#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
10667/******************** Bits definition for RTC_TSDR register *****************/
10668#define RTC_TSDR_WDU_Pos (13U)
10669#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
10670#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
10671#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
10672#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
10673#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
10674#define RTC_TSDR_MT_Pos (12U)
10675#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
10676#define RTC_TSDR_MT RTC_TSDR_MT_Msk
10677#define RTC_TSDR_MU_Pos (8U)
10678#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
10679#define RTC_TSDR_MU RTC_TSDR_MU_Msk
10680#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
10681#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
10682#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
10683#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
10684#define RTC_TSDR_DT_Pos (4U)
10685#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
10686#define RTC_TSDR_DT RTC_TSDR_DT_Msk
10687#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
10688#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
10689#define RTC_TSDR_DU_Pos (0U)
10690#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
10691#define RTC_TSDR_DU RTC_TSDR_DU_Msk
10692#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
10693#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
10694#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
10695#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
10697/******************** Bits definition for RTC_TSSSR register ****************/
10698#define RTC_TSSSR_SS_Pos (0U)
10699#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
10700#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
10701
10702/******************** Bits definition for RTC_CAL register *****************/
10703#define RTC_CALR_CALP_Pos (15U)
10704#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
10705#define RTC_CALR_CALP RTC_CALR_CALP_Msk
10706#define RTC_CALR_CALW8_Pos (14U)
10707#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
10708#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
10709#define RTC_CALR_CALW16_Pos (13U)
10710#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
10711#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
10712#define RTC_CALR_CALM_Pos (0U)
10713#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
10714#define RTC_CALR_CALM RTC_CALR_CALM_Msk
10715#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
10716#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
10717#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
10718#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
10719#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
10720#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
10721#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
10722#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
10723#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
10725/******************** Bits definition for RTC_TAMPCR register ****************/
10726#define RTC_TAMPCR_TAMP3MF_Pos (24U)
10727#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
10728#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
10729#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
10730#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
10731#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
10732#define RTC_TAMPCR_TAMP3IE_Pos (22U)
10733#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
10734#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
10735#define RTC_TAMPCR_TAMP2MF_Pos (21U)
10736#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
10737#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
10738#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
10739#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
10740#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
10741#define RTC_TAMPCR_TAMP2IE_Pos (19U)
10742#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
10743#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
10744#define RTC_TAMPCR_TAMP1MF_Pos (18U)
10745#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
10746#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
10747#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
10748#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
10749#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
10750#define RTC_TAMPCR_TAMP1IE_Pos (16U)
10751#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
10752#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
10753#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
10754#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
10755#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
10756#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
10757#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
10758#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
10759#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
10760#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
10761#define RTC_TAMPCR_TAMPFLT_Pos (11U)
10762#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
10763#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
10764#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
10765#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
10766#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
10767#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
10768#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
10769#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
10770#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
10771#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
10772#define RTC_TAMPCR_TAMPTS_Pos (7U)
10773#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
10774#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
10775#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
10776#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
10777#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
10778#define RTC_TAMPCR_TAMP3E_Pos (5U)
10779#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
10780#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
10781#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
10782#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
10783#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
10784#define RTC_TAMPCR_TAMP2E_Pos (3U)
10785#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
10786#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
10787#define RTC_TAMPCR_TAMPIE_Pos (2U)
10788#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
10789#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
10790#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
10791#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
10792#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
10793#define RTC_TAMPCR_TAMP1E_Pos (0U)
10794#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
10795#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
10796
10797
10798/******************** Bits definition for RTC_ALRMASSR register *************/
10799#define RTC_ALRMASSR_MASKSS_Pos (24U)
10800#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
10801#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
10802#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
10803#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
10804#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
10805#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
10806#define RTC_ALRMASSR_SS_Pos (0U)
10807#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
10808#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
10809
10810/******************** Bits definition for RTC_ALRMBSSR register *************/
10811#define RTC_ALRMBSSR_MASKSS_Pos (24U)
10812#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
10813#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
10814#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
10815#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
10816#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
10817#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
10818#define RTC_ALRMBSSR_SS_Pos (0U)
10819#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
10820#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
10821
10822/******************** Bits definition for RTC_OR register ****************/
10823#define RTC_OR_TSINSEL_Pos (1U)
10824#define RTC_OR_TSINSEL_Msk (0x3UL << RTC_OR_TSINSEL_Pos)
10825#define RTC_OR_TSINSEL RTC_OR_TSINSEL_Msk
10826#define RTC_OR_TSINSEL_0 (0x1UL << RTC_OR_TSINSEL_Pos)
10827#define RTC_OR_TSINSEL_1 (0x2UL << RTC_OR_TSINSEL_Pos)
10828#define RTC_OR_ALARMOUTTYPE_Pos (3U)
10829#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
10830#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
10831/* Legacy defines*/
10832#define RTC_OR_ALARMTYPE RTC_OR_ALARMOUTTYPE
10833
10834/******************** Bits definition for RTC_BKP0R register ****************/
10835#define RTC_BKP0R_Pos (0U)
10836#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
10837#define RTC_BKP0R RTC_BKP0R_Msk
10838
10839/******************** Bits definition for RTC_BKP1R register ****************/
10840#define RTC_BKP1R_Pos (0U)
10841#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
10842#define RTC_BKP1R RTC_BKP1R_Msk
10843
10844/******************** Bits definition for RTC_BKP2R register ****************/
10845#define RTC_BKP2R_Pos (0U)
10846#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
10847#define RTC_BKP2R RTC_BKP2R_Msk
10848
10849/******************** Bits definition for RTC_BKP3R register ****************/
10850#define RTC_BKP3R_Pos (0U)
10851#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
10852#define RTC_BKP3R RTC_BKP3R_Msk
10853
10854/******************** Bits definition for RTC_BKP4R register ****************/
10855#define RTC_BKP4R_Pos (0U)
10856#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
10857#define RTC_BKP4R RTC_BKP4R_Msk
10858
10859/******************** Bits definition for RTC_BKP5R register ****************/
10860#define RTC_BKP5R_Pos (0U)
10861#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
10862#define RTC_BKP5R RTC_BKP5R_Msk
10863
10864/******************** Bits definition for RTC_BKP6R register ****************/
10865#define RTC_BKP6R_Pos (0U)
10866#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
10867#define RTC_BKP6R RTC_BKP6R_Msk
10868
10869/******************** Bits definition for RTC_BKP7R register ****************/
10870#define RTC_BKP7R_Pos (0U)
10871#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
10872#define RTC_BKP7R RTC_BKP7R_Msk
10873
10874/******************** Bits definition for RTC_BKP8R register ****************/
10875#define RTC_BKP8R_Pos (0U)
10876#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
10877#define RTC_BKP8R RTC_BKP8R_Msk
10878
10879/******************** Bits definition for RTC_BKP9R register ****************/
10880#define RTC_BKP9R_Pos (0U)
10881#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
10882#define RTC_BKP9R RTC_BKP9R_Msk
10883
10884/******************** Bits definition for RTC_BKP10R register ***************/
10885#define RTC_BKP10R_Pos (0U)
10886#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
10887#define RTC_BKP10R RTC_BKP10R_Msk
10888
10889/******************** Bits definition for RTC_BKP11R register ***************/
10890#define RTC_BKP11R_Pos (0U)
10891#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
10892#define RTC_BKP11R RTC_BKP11R_Msk
10893
10894/******************** Bits definition for RTC_BKP12R register ***************/
10895#define RTC_BKP12R_Pos (0U)
10896#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
10897#define RTC_BKP12R RTC_BKP12R_Msk
10898
10899/******************** Bits definition for RTC_BKP13R register ***************/
10900#define RTC_BKP13R_Pos (0U)
10901#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
10902#define RTC_BKP13R RTC_BKP13R_Msk
10903
10904/******************** Bits definition for RTC_BKP14R register ***************/
10905#define RTC_BKP14R_Pos (0U)
10906#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
10907#define RTC_BKP14R RTC_BKP14R_Msk
10908
10909/******************** Bits definition for RTC_BKP15R register ***************/
10910#define RTC_BKP15R_Pos (0U)
10911#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
10912#define RTC_BKP15R RTC_BKP15R_Msk
10913
10914/******************** Bits definition for RTC_BKP16R register ***************/
10915#define RTC_BKP16R_Pos (0U)
10916#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
10917#define RTC_BKP16R RTC_BKP16R_Msk
10918
10919/******************** Bits definition for RTC_BKP17R register ***************/
10920#define RTC_BKP17R_Pos (0U)
10921#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
10922#define RTC_BKP17R RTC_BKP17R_Msk
10923
10924/******************** Bits definition for RTC_BKP18R register ***************/
10925#define RTC_BKP18R_Pos (0U)
10926#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
10927#define RTC_BKP18R RTC_BKP18R_Msk
10928
10929/******************** Bits definition for RTC_BKP19R register ***************/
10930#define RTC_BKP19R_Pos (0U)
10931#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
10932#define RTC_BKP19R RTC_BKP19R_Msk
10933
10934/******************** Bits definition for RTC_BKP20R register ***************/
10935#define RTC_BKP20R_Pos (0U)
10936#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
10937#define RTC_BKP20R RTC_BKP20R_Msk
10938
10939/******************** Bits definition for RTC_BKP21R register ***************/
10940#define RTC_BKP21R_Pos (0U)
10941#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
10942#define RTC_BKP21R RTC_BKP21R_Msk
10943
10944/******************** Bits definition for RTC_BKP22R register ***************/
10945#define RTC_BKP22R_Pos (0U)
10946#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
10947#define RTC_BKP22R RTC_BKP22R_Msk
10948
10949/******************** Bits definition for RTC_BKP23R register ***************/
10950#define RTC_BKP23R_Pos (0U)
10951#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
10952#define RTC_BKP23R RTC_BKP23R_Msk
10953
10954/******************** Bits definition for RTC_BKP24R register ***************/
10955#define RTC_BKP24R_Pos (0U)
10956#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
10957#define RTC_BKP24R RTC_BKP24R_Msk
10958
10959/******************** Bits definition for RTC_BKP25R register ***************/
10960#define RTC_BKP25R_Pos (0U)
10961#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
10962#define RTC_BKP25R RTC_BKP25R_Msk
10963
10964/******************** Bits definition for RTC_BKP26R register ***************/
10965#define RTC_BKP26R_Pos (0U)
10966#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
10967#define RTC_BKP26R RTC_BKP26R_Msk
10968
10969/******************** Bits definition for RTC_BKP27R register ***************/
10970#define RTC_BKP27R_Pos (0U)
10971#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
10972#define RTC_BKP27R RTC_BKP27R_Msk
10973
10974/******************** Bits definition for RTC_BKP28R register ***************/
10975#define RTC_BKP28R_Pos (0U)
10976#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
10977#define RTC_BKP28R RTC_BKP28R_Msk
10978
10979/******************** Bits definition for RTC_BKP29R register ***************/
10980#define RTC_BKP29R_Pos (0U)
10981#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
10982#define RTC_BKP29R RTC_BKP29R_Msk
10983
10984/******************** Bits definition for RTC_BKP30R register ***************/
10985#define RTC_BKP30R_Pos (0U)
10986#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
10987#define RTC_BKP30R RTC_BKP30R_Msk
10988
10989/******************** Bits definition for RTC_BKP31R register ***************/
10990#define RTC_BKP31R_Pos (0U)
10991#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
10992#define RTC_BKP31R RTC_BKP31R_Msk
10993
10994/******************** Number of backup registers ******************************/
10995#define RTC_BKP_NUMBER 0x00000020U
10996
10997/******************************************************************************/
10998/* */
10999/* Serial Audio Interface */
11000/* */
11001/******************************************************************************/
11002/******************** Bit definition for SAI_GCR register *******************/
11003#define SAI_GCR_SYNCIN_Pos (0U)
11004#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
11005#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
11006#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
11007#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
11009#define SAI_GCR_SYNCOUT_Pos (4U)
11010#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
11011#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
11012#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
11013#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
11015/******************* Bit definition for SAI_xCR1 register *******************/
11016#define SAI_xCR1_MODE_Pos (0U)
11017#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
11018#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
11019#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
11020#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
11022#define SAI_xCR1_PRTCFG_Pos (2U)
11023#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
11024#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
11025#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
11026#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
11028#define SAI_xCR1_DS_Pos (5U)
11029#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
11030#define SAI_xCR1_DS SAI_xCR1_DS_Msk
11031#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
11032#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
11033#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
11035#define SAI_xCR1_LSBFIRST_Pos (8U)
11036#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
11037#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
11038#define SAI_xCR1_CKSTR_Pos (9U)
11039#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
11040#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
11042#define SAI_xCR1_SYNCEN_Pos (10U)
11043#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
11044#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
11045#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
11046#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
11048#define SAI_xCR1_MONO_Pos (12U)
11049#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
11050#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
11051#define SAI_xCR1_OUTDRIV_Pos (13U)
11052#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
11053#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
11054#define SAI_xCR1_SAIEN_Pos (16U)
11055#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
11056#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
11057#define SAI_xCR1_DMAEN_Pos (17U)
11058#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
11059#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
11060#define SAI_xCR1_NODIV_Pos (19U)
11061#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
11062#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
11064#define SAI_xCR1_MCKDIV_Pos (20U)
11065#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos)
11066#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
11067#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos)
11068#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos)
11069#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos)
11070#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos)
11072/******************* Bit definition for SAI_xCR2 register *******************/
11073#define SAI_xCR2_FTH_Pos (0U)
11074#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
11075#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
11076#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
11077#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
11078#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
11080#define SAI_xCR2_FFLUSH_Pos (3U)
11081#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
11082#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
11083#define SAI_xCR2_TRIS_Pos (4U)
11084#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
11085#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
11086#define SAI_xCR2_MUTE_Pos (5U)
11087#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
11088#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
11089#define SAI_xCR2_MUTEVAL_Pos (6U)
11090#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
11091#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
11093#define SAI_xCR2_MUTECNT_Pos (7U)
11094#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
11095#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
11096#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
11097#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
11098#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
11099#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
11100#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
11101#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
11103#define SAI_xCR2_CPL_Pos (13U)
11104#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
11105#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
11107#define SAI_xCR2_COMP_Pos (14U)
11108#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
11109#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
11110#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
11111#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
11113/****************** Bit definition for SAI_xFRCR register *******************/
11114#define SAI_xFRCR_FRL_Pos (0U)
11115#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
11116#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
11117#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
11118#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
11119#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
11120#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
11121#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
11122#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
11123#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
11124#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
11126#define SAI_xFRCR_FSALL_Pos (8U)
11127#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
11128#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
11129#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
11130#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
11131#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
11132#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
11133#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
11134#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
11135#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
11137#define SAI_xFRCR_FSDEF_Pos (16U)
11138#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
11139#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
11140#define SAI_xFRCR_FSPOL_Pos (17U)
11141#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
11142#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
11143#define SAI_xFRCR_FSOFF_Pos (18U)
11144#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
11145#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
11147/* Legacy define */
11148#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
11149
11150/****************** Bit definition for SAI_xSLOTR register *******************/
11151#define SAI_xSLOTR_FBOFF_Pos (0U)
11152#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
11153#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
11154#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
11155#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
11156#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
11157#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
11158#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
11160#define SAI_xSLOTR_SLOTSZ_Pos (6U)
11161#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
11162#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
11163#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
11164#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
11166#define SAI_xSLOTR_NBSLOT_Pos (8U)
11167#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
11168#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
11169#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
11170#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
11171#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
11172#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
11174#define SAI_xSLOTR_SLOTEN_Pos (16U)
11175#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
11176#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
11178/******************* Bit definition for SAI_xIMR register *******************/
11179#define SAI_xIMR_OVRUDRIE_Pos (0U)
11180#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
11181#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
11182#define SAI_xIMR_MUTEDETIE_Pos (1U)
11183#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
11184#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
11185#define SAI_xIMR_WCKCFGIE_Pos (2U)
11186#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
11187#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
11188#define SAI_xIMR_FREQIE_Pos (3U)
11189#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
11190#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
11191#define SAI_xIMR_CNRDYIE_Pos (4U)
11192#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
11193#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
11194#define SAI_xIMR_AFSDETIE_Pos (5U)
11195#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
11196#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
11197#define SAI_xIMR_LFSDETIE_Pos (6U)
11198#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
11199#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
11201/******************** Bit definition for SAI_xSR register *******************/
11202#define SAI_xSR_OVRUDR_Pos (0U)
11203#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
11204#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
11205#define SAI_xSR_MUTEDET_Pos (1U)
11206#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
11207#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
11208#define SAI_xSR_WCKCFG_Pos (2U)
11209#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
11210#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
11211#define SAI_xSR_FREQ_Pos (3U)
11212#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
11213#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
11214#define SAI_xSR_CNRDY_Pos (4U)
11215#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
11216#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
11217#define SAI_xSR_AFSDET_Pos (5U)
11218#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
11219#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
11220#define SAI_xSR_LFSDET_Pos (6U)
11221#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
11222#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
11224#define SAI_xSR_FLVL_Pos (16U)
11225#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
11226#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
11227#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
11228#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
11229#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
11231/****************** Bit definition for SAI_xCLRFR register ******************/
11232#define SAI_xCLRFR_COVRUDR_Pos (0U)
11233#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
11234#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
11235#define SAI_xCLRFR_CMUTEDET_Pos (1U)
11236#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
11237#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
11238#define SAI_xCLRFR_CWCKCFG_Pos (2U)
11239#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
11240#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
11241#define SAI_xCLRFR_CFREQ_Pos (3U)
11242#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
11243#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
11244#define SAI_xCLRFR_CCNRDY_Pos (4U)
11245#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
11246#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
11247#define SAI_xCLRFR_CAFSDET_Pos (5U)
11248#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
11249#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
11250#define SAI_xCLRFR_CLFSDET_Pos (6U)
11251#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
11252#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
11254/****************** Bit definition for SAI_xDR register *********************/
11255#define SAI_xDR_DATA_Pos (0U)
11256#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
11257#define SAI_xDR_DATA SAI_xDR_DATA_Msk
11258
11259
11260/******************************************************************************/
11261/* */
11262/* SD host Interface */
11263/* */
11264/******************************************************************************/
11265/****************** Bit definition for SDMMC_POWER register ******************/
11266#define SDMMC_POWER_PWRCTRL_Pos (0U)
11267#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
11268#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
11269#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
11270#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
11272/****************** Bit definition for SDMMC_CLKCR register ******************/
11273#define SDMMC_CLKCR_CLKDIV_Pos (0U)
11274#define SDMMC_CLKCR_CLKDIV_Msk (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos)
11275#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
11276#define SDMMC_CLKCR_CLKEN_Pos (8U)
11277#define SDMMC_CLKCR_CLKEN_Msk (0x1UL << SDMMC_CLKCR_CLKEN_Pos)
11278#define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk
11279#define SDMMC_CLKCR_PWRSAV_Pos (9U)
11280#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
11281#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
11282#define SDMMC_CLKCR_BYPASS_Pos (10U)
11283#define SDMMC_CLKCR_BYPASS_Msk (0x1UL << SDMMC_CLKCR_BYPASS_Pos)
11284#define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk
11286#define SDMMC_CLKCR_WIDBUS_Pos (11U)
11287#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
11288#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
11289#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
11290#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
11292#define SDMMC_CLKCR_NEGEDGE_Pos (13U)
11293#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
11294#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
11295#define SDMMC_CLKCR_HWFC_EN_Pos (14U)
11296#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
11297#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
11299/******************* Bit definition for SDMMC_ARG register *******************/
11300#define SDMMC_ARG_CMDARG_Pos (0U)
11301#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
11302#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
11304/******************* Bit definition for SDMMC_CMD register *******************/
11305#define SDMMC_CMD_CMDINDEX_Pos (0U)
11306#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
11307#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
11309#define SDMMC_CMD_WAITRESP_Pos (6U)
11310#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
11311#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
11312#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
11313#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
11315#define SDMMC_CMD_WAITINT_Pos (8U)
11316#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
11317#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
11318#define SDMMC_CMD_WAITPEND_Pos (9U)
11319#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
11320#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
11321#define SDMMC_CMD_CPSMEN_Pos (10U)
11322#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
11323#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
11324#define SDMMC_CMD_SDIOSUSPEND_Pos (11U)
11325#define SDMMC_CMD_SDIOSUSPEND_Msk (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos)
11326#define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk
11328/***************** Bit definition for SDMMC_RESPCMD register *****************/
11329#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
11330#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
11331#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
11333/****************** Bit definition for SDMMC_RESP0 register ******************/
11334#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
11335#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos)
11336#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk
11338/****************** Bit definition for SDMMC_RESP1 register ******************/
11339#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
11340#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
11341#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
11343/****************** Bit definition for SDMMC_RESP2 register ******************/
11344#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
11345#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
11346#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
11348/****************** Bit definition for SDMMC_RESP3 register ******************/
11349#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
11350#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
11351#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
11353/****************** Bit definition for SDMMC_RESP4 register ******************/
11354#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
11355#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
11356#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
11358/****************** Bit definition for SDMMC_DTIMER register *****************/
11359#define SDMMC_DTIMER_DATATIME_Pos (0U)
11360#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
11361#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
11363/****************** Bit definition for SDMMC_DLEN register *******************/
11364#define SDMMC_DLEN_DATALENGTH_Pos (0U)
11365#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
11366#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
11368/****************** Bit definition for SDMMC_DCTRL register ******************/
11369#define SDMMC_DCTRL_DTEN_Pos (0U)
11370#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
11371#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
11372#define SDMMC_DCTRL_DTDIR_Pos (1U)
11373#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
11374#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
11375#define SDMMC_DCTRL_DTMODE_Pos (2U)
11376#define SDMMC_DCTRL_DTMODE_Msk (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
11377#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
11378#define SDMMC_DCTRL_DMAEN_Pos (3U)
11379#define SDMMC_DCTRL_DMAEN_Msk (0x1UL << SDMMC_DCTRL_DMAEN_Pos)
11380#define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk
11382#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
11383#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
11384#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
11385#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
11386#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
11387#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
11388#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
11390#define SDMMC_DCTRL_RWSTART_Pos (8U)
11391#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
11392#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
11393#define SDMMC_DCTRL_RWSTOP_Pos (9U)
11394#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
11395#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
11396#define SDMMC_DCTRL_RWMOD_Pos (10U)
11397#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
11398#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
11399#define SDMMC_DCTRL_SDIOEN_Pos (11U)
11400#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
11401#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
11403/****************** Bit definition for SDMMC_DCOUNT register *****************/
11404#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
11405#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
11406#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
11408/****************** Bit definition for SDMMC_STA registe ********************/
11409#define SDMMC_STA_CCRCFAIL_Pos (0U)
11410#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
11411#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
11412#define SDMMC_STA_DCRCFAIL_Pos (1U)
11413#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
11414#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
11415#define SDMMC_STA_CTIMEOUT_Pos (2U)
11416#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
11417#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
11418#define SDMMC_STA_DTIMEOUT_Pos (3U)
11419#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
11420#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
11421#define SDMMC_STA_TXUNDERR_Pos (4U)
11422#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
11423#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
11424#define SDMMC_STA_RXOVERR_Pos (5U)
11425#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
11426#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
11427#define SDMMC_STA_CMDREND_Pos (6U)
11428#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
11429#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
11430#define SDMMC_STA_CMDSENT_Pos (7U)
11431#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
11432#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
11433#define SDMMC_STA_DATAEND_Pos (8U)
11434#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
11435#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
11436#define SDMMC_STA_DBCKEND_Pos (10U)
11437#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
11438#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
11439#define SDMMC_STA_CMDACT_Pos (11U)
11440#define SDMMC_STA_CMDACT_Msk (0x1UL << SDMMC_STA_CMDACT_Pos)
11441#define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk
11442#define SDMMC_STA_TXACT_Pos (12U)
11443#define SDMMC_STA_TXACT_Msk (0x1UL << SDMMC_STA_TXACT_Pos)
11444#define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk
11445#define SDMMC_STA_RXACT_Pos (13U)
11446#define SDMMC_STA_RXACT_Msk (0x1UL << SDMMC_STA_RXACT_Pos)
11447#define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk
11448#define SDMMC_STA_TXFIFOHE_Pos (14U)
11449#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
11450#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
11451#define SDMMC_STA_RXFIFOHF_Pos (15U)
11452#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
11453#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
11454#define SDMMC_STA_TXFIFOF_Pos (16U)
11455#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
11456#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
11457#define SDMMC_STA_RXFIFOF_Pos (17U)
11458#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
11459#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
11460#define SDMMC_STA_TXFIFOE_Pos (18U)
11461#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
11462#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
11463#define SDMMC_STA_RXFIFOE_Pos (19U)
11464#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
11465#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
11466#define SDMMC_STA_TXDAVL_Pos (20U)
11467#define SDMMC_STA_TXDAVL_Msk (0x1UL << SDMMC_STA_TXDAVL_Pos)
11468#define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk
11469#define SDMMC_STA_RXDAVL_Pos (21U)
11470#define SDMMC_STA_RXDAVL_Msk (0x1UL << SDMMC_STA_RXDAVL_Pos)
11471#define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk
11472#define SDMMC_STA_SDIOIT_Pos (22U)
11473#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
11474#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
11476/******************* Bit definition for SDMMC_ICR register *******************/
11477#define SDMMC_ICR_CCRCFAILC_Pos (0U)
11478#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
11479#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
11480#define SDMMC_ICR_DCRCFAILC_Pos (1U)
11481#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
11482#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
11483#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
11484#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
11485#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
11486#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
11487#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
11488#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
11489#define SDMMC_ICR_TXUNDERRC_Pos (4U)
11490#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
11491#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
11492#define SDMMC_ICR_RXOVERRC_Pos (5U)
11493#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
11494#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
11495#define SDMMC_ICR_CMDRENDC_Pos (6U)
11496#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
11497#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
11498#define SDMMC_ICR_CMDSENTC_Pos (7U)
11499#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
11500#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
11501#define SDMMC_ICR_DATAENDC_Pos (8U)
11502#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
11503#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
11504#define SDMMC_ICR_DBCKENDC_Pos (10U)
11505#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
11506#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
11507#define SDMMC_ICR_SDIOITC_Pos (22U)
11508#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
11509#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
11511/****************** Bit definition for SDMMC_MASK register *******************/
11512#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
11513#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
11514#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
11515#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
11516#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
11517#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
11518#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
11519#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
11520#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
11521#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
11522#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
11523#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
11524#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
11525#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
11526#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
11527#define SDMMC_MASK_RXOVERRIE_Pos (5U)
11528#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
11529#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
11530#define SDMMC_MASK_CMDRENDIE_Pos (6U)
11531#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
11532#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
11533#define SDMMC_MASK_CMDSENTIE_Pos (7U)
11534#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
11535#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
11536#define SDMMC_MASK_DATAENDIE_Pos (8U)
11537#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
11538#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
11539#define SDMMC_MASK_DBCKENDIE_Pos (10U)
11540#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
11541#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
11542#define SDMMC_MASK_CMDACTIE_Pos (11U)
11543#define SDMMC_MASK_CMDACTIE_Msk (0x1UL << SDMMC_MASK_CMDACTIE_Pos)
11544#define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk
11545#define SDMMC_MASK_TXACTIE_Pos (12U)
11546#define SDMMC_MASK_TXACTIE_Msk (0x1UL << SDMMC_MASK_TXACTIE_Pos)
11547#define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk
11548#define SDMMC_MASK_RXACTIE_Pos (13U)
11549#define SDMMC_MASK_RXACTIE_Msk (0x1UL << SDMMC_MASK_RXACTIE_Pos)
11550#define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk
11551#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
11552#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
11553#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
11554#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
11555#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
11556#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
11557#define SDMMC_MASK_TXFIFOFIE_Pos (16U)
11558#define SDMMC_MASK_TXFIFOFIE_Msk (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos)
11559#define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk
11560#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
11561#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
11562#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
11563#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
11564#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
11565#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
11566#define SDMMC_MASK_RXFIFOEIE_Pos (19U)
11567#define SDMMC_MASK_RXFIFOEIE_Msk (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos)
11568#define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk
11569#define SDMMC_MASK_TXDAVLIE_Pos (20U)
11570#define SDMMC_MASK_TXDAVLIE_Msk (0x1UL << SDMMC_MASK_TXDAVLIE_Pos)
11571#define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk
11572#define SDMMC_MASK_RXDAVLIE_Pos (21U)
11573#define SDMMC_MASK_RXDAVLIE_Msk (0x1UL << SDMMC_MASK_RXDAVLIE_Pos)
11574#define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk
11575#define SDMMC_MASK_SDIOITIE_Pos (22U)
11576#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
11577#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
11579/***************** Bit definition for SDMMC_FIFOCNT register *****************/
11580#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)
11581#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos)
11582#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk
11584/****************** Bit definition for SDMMC_FIFO register *******************/
11585#define SDMMC_FIFO_FIFODATA_Pos (0U)
11586#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
11587#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
11589/******************************************************************************/
11590/* */
11591/* Serial Peripheral Interface (SPI) */
11592/* */
11593/******************************************************************************/
11594/******************* Bit definition for SPI_CR1 register ********************/
11595#define SPI_CR1_CPHA_Pos (0U)
11596#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
11597#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
11598#define SPI_CR1_CPOL_Pos (1U)
11599#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
11600#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
11601#define SPI_CR1_MSTR_Pos (2U)
11602#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
11603#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
11604#define SPI_CR1_BR_Pos (3U)
11605#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
11606#define SPI_CR1_BR SPI_CR1_BR_Msk
11607#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
11608#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
11609#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
11610#define SPI_CR1_SPE_Pos (6U)
11611#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
11612#define SPI_CR1_SPE SPI_CR1_SPE_Msk
11613#define SPI_CR1_LSBFIRST_Pos (7U)
11614#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
11615#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
11616#define SPI_CR1_SSI_Pos (8U)
11617#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
11618#define SPI_CR1_SSI SPI_CR1_SSI_Msk
11619#define SPI_CR1_SSM_Pos (9U)
11620#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
11621#define SPI_CR1_SSM SPI_CR1_SSM_Msk
11622#define SPI_CR1_RXONLY_Pos (10U)
11623#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
11624#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
11625#define SPI_CR1_CRCL_Pos (11U)
11626#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos)
11627#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk
11628#define SPI_CR1_CRCNEXT_Pos (12U)
11629#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
11630#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
11631#define SPI_CR1_CRCEN_Pos (13U)
11632#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
11633#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
11634#define SPI_CR1_BIDIOE_Pos (14U)
11635#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
11636#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
11637#define SPI_CR1_BIDIMODE_Pos (15U)
11638#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
11639#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
11641/******************* Bit definition for SPI_CR2 register ********************/
11642#define SPI_CR2_RXDMAEN_Pos (0U)
11643#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
11644#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
11645#define SPI_CR2_TXDMAEN_Pos (1U)
11646#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
11647#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
11648#define SPI_CR2_SSOE_Pos (2U)
11649#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
11650#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
11651#define SPI_CR2_NSSP_Pos (3U)
11652#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos)
11653#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk
11654#define SPI_CR2_FRF_Pos (4U)
11655#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos)
11656#define SPI_CR2_FRF SPI_CR2_FRF_Msk
11657#define SPI_CR2_ERRIE_Pos (5U)
11658#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
11659#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
11660#define SPI_CR2_RXNEIE_Pos (6U)
11661#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
11662#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
11663#define SPI_CR2_TXEIE_Pos (7U)
11664#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
11665#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
11666#define SPI_CR2_DS_Pos (8U)
11667#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos)
11668#define SPI_CR2_DS SPI_CR2_DS_Msk
11669#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos)
11670#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos)
11671#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos)
11672#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos)
11673#define SPI_CR2_FRXTH_Pos (12U)
11674#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos)
11675#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk
11676#define SPI_CR2_LDMARX_Pos (13U)
11677#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos)
11678#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk
11679#define SPI_CR2_LDMATX_Pos (14U)
11680#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos)
11681#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk
11683/******************** Bit definition for SPI_SR register ********************/
11684#define SPI_SR_RXNE_Pos (0U)
11685#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
11686#define SPI_SR_RXNE SPI_SR_RXNE_Msk
11687#define SPI_SR_TXE_Pos (1U)
11688#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
11689#define SPI_SR_TXE SPI_SR_TXE_Msk
11690#define SPI_SR_CHSIDE_Pos (2U)
11691#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
11692#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
11693#define SPI_SR_UDR_Pos (3U)
11694#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
11695#define SPI_SR_UDR SPI_SR_UDR_Msk
11696#define SPI_SR_CRCERR_Pos (4U)
11697#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
11698#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
11699#define SPI_SR_MODF_Pos (5U)
11700#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
11701#define SPI_SR_MODF SPI_SR_MODF_Msk
11702#define SPI_SR_OVR_Pos (6U)
11703#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
11704#define SPI_SR_OVR SPI_SR_OVR_Msk
11705#define SPI_SR_BSY_Pos (7U)
11706#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
11707#define SPI_SR_BSY SPI_SR_BSY_Msk
11708#define SPI_SR_FRE_Pos (8U)
11709#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos)
11710#define SPI_SR_FRE SPI_SR_FRE_Msk
11711#define SPI_SR_FRLVL_Pos (9U)
11712#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos)
11713#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk
11714#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos)
11715#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos)
11716#define SPI_SR_FTLVL_Pos (11U)
11717#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos)
11718#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk
11719#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos)
11720#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos)
11722/******************** Bit definition for SPI_DR register ********************/
11723#define SPI_DR_DR_Pos (0U)
11724#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
11725#define SPI_DR_DR SPI_DR_DR_Msk
11727/******************* Bit definition for SPI_CRCPR register ******************/
11728#define SPI_CRCPR_CRCPOLY_Pos (0U)
11729#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
11730#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
11732/****************** Bit definition for SPI_RXCRCR register ******************/
11733#define SPI_RXCRCR_RXCRC_Pos (0U)
11734#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
11735#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
11737/****************** Bit definition for SPI_TXCRCR register ******************/
11738#define SPI_TXCRCR_TXCRC_Pos (0U)
11739#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
11740#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
11742/****************** Bit definition for SPI_I2SCFGR register *****************/
11743#define SPI_I2SCFGR_CHLEN_Pos (0U)
11744#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
11745#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
11746#define SPI_I2SCFGR_DATLEN_Pos (1U)
11747#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
11748#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
11749#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
11750#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
11751#define SPI_I2SCFGR_CKPOL_Pos (3U)
11752#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
11753#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
11754#define SPI_I2SCFGR_I2SSTD_Pos (4U)
11755#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
11756#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
11757#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
11758#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
11759#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
11760#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
11761#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
11762#define SPI_I2SCFGR_I2SCFG_Pos (8U)
11763#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)
11764#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
11765#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
11766#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
11767#define SPI_I2SCFGR_I2SE_Pos (10U)
11768#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)
11769#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk
11770#define SPI_I2SCFGR_I2SMOD_Pos (11U)
11771#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
11772#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
11773#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
11774#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)
11775#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk
11777/****************** Bit definition for SPI_I2SPR register *******************/
11778#define SPI_I2SPR_I2SDIV_Pos (0U)
11779#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)
11780#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk
11781#define SPI_I2SPR_ODD_Pos (8U)
11782#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)
11783#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk
11784#define SPI_I2SPR_MCKOE_Pos (9U)
11785#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)
11786#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk
11789/******************************************************************************/
11790/* */
11791/* SYSCFG */
11792/* */
11793/******************************************************************************/
11794/****************** Bit definition for SYSCFG_MEMRMP register ***************/
11795#define SYSCFG_MEMRMP_MEM_BOOT_Pos (0U)
11796#define SYSCFG_MEMRMP_MEM_BOOT_Msk (0x1UL << SYSCFG_MEMRMP_MEM_BOOT_Pos)
11797#define SYSCFG_MEMRMP_MEM_BOOT SYSCFG_MEMRMP_MEM_BOOT_Msk
11800#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
11801#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
11802#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk
11803#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
11804#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos)
11806/****************** Bit definition for SYSCFG_PMC register ******************/
11807#define SYSCFG_PMC_I2C1_FMP_Pos (0U)
11808#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos)
11809#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk
11810#define SYSCFG_PMC_I2C2_FMP_Pos (1U)
11811#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos)
11812#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk
11813#define SYSCFG_PMC_I2C3_FMP_Pos (2U)
11814#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos)
11815#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk
11816#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)
11817#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos)
11818#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk
11819#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)
11820#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos)
11821#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk
11822#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)
11823#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos)
11824#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk
11825#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)
11826#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos)
11827#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk
11829#define SYSCFG_PMC_ADCxDC2_Pos (16U)
11830#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos)
11831#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk
11832#define SYSCFG_PMC_ADC1DC2_Pos (16U)
11833#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos)
11834#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk
11835#define SYSCFG_PMC_ADC2DC2_Pos (17U)
11836#define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos)
11837#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk
11838#define SYSCFG_PMC_ADC3DC2_Pos (18U)
11839#define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos)
11840#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk
11843/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
11844#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
11845#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
11846#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
11847#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
11848#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
11849#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
11850#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
11851#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
11852#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
11853#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
11854#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
11855#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
11859#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U
11860#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U
11861#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U
11862#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U
11863#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U
11864#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U
11865#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U
11866#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U
11867#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U
11868#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U
11869#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU
11874#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U
11875#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U
11876#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U
11877#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U
11878#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U
11879#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U
11880#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U
11881#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U
11882#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U
11883#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U
11884#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U
11889#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U
11890#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U
11891#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U
11892#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U
11893#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U
11894#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U
11895#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U
11896#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U
11897#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U
11898#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U
11899#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U
11904#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U
11905#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U
11906#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U
11907#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U
11908#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U
11909#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U
11910#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U
11911#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U
11912#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U
11913#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U
11914#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U
11916/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
11917#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
11918#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
11919#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
11920#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
11921#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
11922#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
11923#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
11924#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
11925#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
11926#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
11927#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
11928#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
11932#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U
11933#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U
11934#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U
11935#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U
11936#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U
11937#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U
11938#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U
11939#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U
11940#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U
11941#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U
11942#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU
11947#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U
11948#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U
11949#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U
11950#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U
11951#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U
11952#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U
11953#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U
11954#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U
11955#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U
11956#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U
11957#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U
11962#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U
11963#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U
11964#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U
11965#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U
11966#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U
11967#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U
11968#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U
11969#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U
11970#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U
11971#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U
11972#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U
11977#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U
11978#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U
11979#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U
11980#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U
11981#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U
11982#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U
11983#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U
11984#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U
11985#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U
11986#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U
11987#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U
11989/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
11990#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
11991#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
11992#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
11993#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
11994#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
11995#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
11996#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
11997#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
11998#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
11999#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
12000#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
12001#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
12006#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U
12007#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U
12008#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U
12009#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U
12010#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U
12011#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U
12012#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U
12013#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U
12014#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U
12015#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U
12020#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U
12021#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U
12022#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U
12023#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U
12024#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U
12025#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U
12026#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U
12027#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U
12028#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U
12029#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U
12034#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U
12035#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U
12036#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U
12037#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U
12038#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U
12039#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U
12040#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U
12041#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U
12042#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U
12043#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U
12048#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U
12049#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U
12050#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U
12051#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U
12052#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U
12053#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U
12054#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U
12055#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U
12056#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U
12057#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U
12060/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
12061#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
12062#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
12063#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
12064#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
12065#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
12066#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
12067#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
12068#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
12069#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
12070#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
12071#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
12072#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
12076#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U
12077#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U
12078#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U
12079#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U
12080#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U
12081#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U
12082#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U
12083#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U
12084#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U
12085#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U
12090#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U
12091#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U
12092#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U
12093#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U
12094#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U
12095#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U
12096#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U
12097#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U
12098#define SYSCFG_EXTICR4_EXTI13_PI 0x0080U
12099#define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U
12104#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U
12105#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U
12106#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U
12107#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U
12108#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U
12109#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U
12110#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U
12111#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U
12112#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U
12113#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U
12118#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U
12119#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U
12120#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U
12121#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U
12122#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U
12123#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U
12124#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U
12125#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U
12126#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U
12127#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U
12130/****************** Bit definition for SYSCFG_CMPCR register ****************/
12131#define SYSCFG_CMPCR_CMP_PD_Pos (0U)
12132#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos)
12133#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk
12134#define SYSCFG_CMPCR_READY_Pos (8U)
12135#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos)
12136#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk
12138/******************************************************************************/
12139/* */
12140/* TIM */
12141/* */
12142/******************************************************************************/
12143/******************* Bit definition for TIM_CR1 register ********************/
12144#define TIM_CR1_CEN_Pos (0U)
12145#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
12146#define TIM_CR1_CEN TIM_CR1_CEN_Msk
12147#define TIM_CR1_UDIS_Pos (1U)
12148#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
12149#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
12150#define TIM_CR1_URS_Pos (2U)
12151#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
12152#define TIM_CR1_URS TIM_CR1_URS_Msk
12153#define TIM_CR1_OPM_Pos (3U)
12154#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
12155#define TIM_CR1_OPM TIM_CR1_OPM_Msk
12156#define TIM_CR1_DIR_Pos (4U)
12157#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
12158#define TIM_CR1_DIR TIM_CR1_DIR_Msk
12160#define TIM_CR1_CMS_Pos (5U)
12161#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
12162#define TIM_CR1_CMS TIM_CR1_CMS_Msk
12163#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
12164#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
12166#define TIM_CR1_ARPE_Pos (7U)
12167#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
12168#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
12170#define TIM_CR1_CKD_Pos (8U)
12171#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
12172#define TIM_CR1_CKD TIM_CR1_CKD_Msk
12173#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
12174#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
12175#define TIM_CR1_UIFREMAP_Pos (11U)
12176#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
12177#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
12179/******************* Bit definition for TIM_CR2 register ********************/
12180#define TIM_CR2_CCPC_Pos (0U)
12181#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
12182#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
12183#define TIM_CR2_CCUS_Pos (2U)
12184#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
12185#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
12186#define TIM_CR2_CCDS_Pos (3U)
12187#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
12188#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
12190#define TIM_CR2_OIS5_Pos (16U)
12191#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
12192#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
12193#define TIM_CR2_OIS6_Pos (18U)
12194#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
12195#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
12197#define TIM_CR2_MMS_Pos (4U)
12198#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
12199#define TIM_CR2_MMS TIM_CR2_MMS_Msk
12200#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
12201#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
12202#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
12204#define TIM_CR2_MMS2_Pos (20U)
12205#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
12206#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
12207#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
12208#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
12209#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
12210#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
12212#define TIM_CR2_TI1S_Pos (7U)
12213#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
12214#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
12215#define TIM_CR2_OIS1_Pos (8U)
12216#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
12217#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
12218#define TIM_CR2_OIS1N_Pos (9U)
12219#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
12220#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
12221#define TIM_CR2_OIS2_Pos (10U)
12222#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
12223#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
12224#define TIM_CR2_OIS2N_Pos (11U)
12225#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
12226#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
12227#define TIM_CR2_OIS3_Pos (12U)
12228#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
12229#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
12230#define TIM_CR2_OIS3N_Pos (13U)
12231#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
12232#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
12233#define TIM_CR2_OIS4_Pos (14U)
12234#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
12235#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
12237/******************* Bit definition for TIM_SMCR register *******************/
12238#define TIM_SMCR_SMS_Pos (0U)
12239#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
12240#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
12241#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
12242#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
12243#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
12244#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
12246#define TIM_SMCR_TS_Pos (4U)
12247#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
12248#define TIM_SMCR_TS TIM_SMCR_TS_Msk
12249#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
12250#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
12251#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
12253#define TIM_SMCR_MSM_Pos (7U)
12254#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
12255#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
12257#define TIM_SMCR_ETF_Pos (8U)
12258#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
12259#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
12260#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
12261#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
12262#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
12263#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
12265#define TIM_SMCR_ETPS_Pos (12U)
12266#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
12267#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
12268#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
12269#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
12271#define TIM_SMCR_ECE_Pos (14U)
12272#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
12273#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
12274#define TIM_SMCR_ETP_Pos (15U)
12275#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
12276#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
12278/******************* Bit definition for TIM_DIER register *******************/
12279#define TIM_DIER_UIE_Pos (0U)
12280#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
12281#define TIM_DIER_UIE TIM_DIER_UIE_Msk
12282#define TIM_DIER_CC1IE_Pos (1U)
12283#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
12284#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
12285#define TIM_DIER_CC2IE_Pos (2U)
12286#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
12287#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
12288#define TIM_DIER_CC3IE_Pos (3U)
12289#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
12290#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
12291#define TIM_DIER_CC4IE_Pos (4U)
12292#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
12293#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
12294#define TIM_DIER_COMIE_Pos (5U)
12295#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
12296#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
12297#define TIM_DIER_TIE_Pos (6U)
12298#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
12299#define TIM_DIER_TIE TIM_DIER_TIE_Msk
12300#define TIM_DIER_BIE_Pos (7U)
12301#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
12302#define TIM_DIER_BIE TIM_DIER_BIE_Msk
12303#define TIM_DIER_UDE_Pos (8U)
12304#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
12305#define TIM_DIER_UDE TIM_DIER_UDE_Msk
12306#define TIM_DIER_CC1DE_Pos (9U)
12307#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
12308#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
12309#define TIM_DIER_CC2DE_Pos (10U)
12310#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
12311#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
12312#define TIM_DIER_CC3DE_Pos (11U)
12313#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
12314#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
12315#define TIM_DIER_CC4DE_Pos (12U)
12316#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
12317#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
12318#define TIM_DIER_COMDE_Pos (13U)
12319#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
12320#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
12321#define TIM_DIER_TDE_Pos (14U)
12322#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
12323#define TIM_DIER_TDE TIM_DIER_TDE_Msk
12325/******************** Bit definition for TIM_SR register ********************/
12326#define TIM_SR_UIF_Pos (0U)
12327#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
12328#define TIM_SR_UIF TIM_SR_UIF_Msk
12329#define TIM_SR_CC1IF_Pos (1U)
12330#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
12331#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
12332#define TIM_SR_CC2IF_Pos (2U)
12333#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
12334#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
12335#define TIM_SR_CC3IF_Pos (3U)
12336#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
12337#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
12338#define TIM_SR_CC4IF_Pos (4U)
12339#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
12340#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
12341#define TIM_SR_COMIF_Pos (5U)
12342#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
12343#define TIM_SR_COMIF TIM_SR_COMIF_Msk
12344#define TIM_SR_TIF_Pos (6U)
12345#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
12346#define TIM_SR_TIF TIM_SR_TIF_Msk
12347#define TIM_SR_BIF_Pos (7U)
12348#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
12349#define TIM_SR_BIF TIM_SR_BIF_Msk
12350#define TIM_SR_B2IF_Pos (8U)
12351#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
12352#define TIM_SR_B2IF TIM_SR_B2IF_Msk
12353#define TIM_SR_CC1OF_Pos (9U)
12354#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
12355#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
12356#define TIM_SR_CC2OF_Pos (10U)
12357#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
12358#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
12359#define TIM_SR_CC3OF_Pos (11U)
12360#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
12361#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
12362#define TIM_SR_CC4OF_Pos (12U)
12363#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
12364#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
12365#define TIM_SR_SBIF_Pos (13U)
12366#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
12367#define TIM_SR_SBIF TIM_SR_SBIF_Msk
12368#define TIM_SR_CC5IF_Pos (16U)
12369#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
12370#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
12371#define TIM_SR_CC6IF_Pos (17U)
12372#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
12373#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
12375/******************* Bit definition for TIM_EGR register ********************/
12376#define TIM_EGR_UG_Pos (0U)
12377#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
12378#define TIM_EGR_UG TIM_EGR_UG_Msk
12379#define TIM_EGR_CC1G_Pos (1U)
12380#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
12381#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
12382#define TIM_EGR_CC2G_Pos (2U)
12383#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
12384#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
12385#define TIM_EGR_CC3G_Pos (3U)
12386#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
12387#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
12388#define TIM_EGR_CC4G_Pos (4U)
12389#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
12390#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
12391#define TIM_EGR_COMG_Pos (5U)
12392#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
12393#define TIM_EGR_COMG TIM_EGR_COMG_Msk
12394#define TIM_EGR_TG_Pos (6U)
12395#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
12396#define TIM_EGR_TG TIM_EGR_TG_Msk
12397#define TIM_EGR_BG_Pos (7U)
12398#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
12399#define TIM_EGR_BG TIM_EGR_BG_Msk
12400#define TIM_EGR_B2G_Pos (8U)
12401#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
12402#define TIM_EGR_B2G TIM_EGR_B2G_Msk
12404/****************** Bit definition for TIM_CCMR1 register *******************/
12405#define TIM_CCMR1_CC1S_Pos (0U)
12406#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
12407#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
12408#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
12409#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
12411#define TIM_CCMR1_OC1FE_Pos (2U)
12412#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
12413#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
12414#define TIM_CCMR1_OC1PE_Pos (3U)
12415#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
12416#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
12418#define TIM_CCMR1_OC1M_Pos (4U)
12419#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
12420#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
12421#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
12422#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
12423#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
12424#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
12426#define TIM_CCMR1_OC1CE_Pos (7U)
12427#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
12428#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
12430#define TIM_CCMR1_CC2S_Pos (8U)
12431#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
12432#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
12433#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
12434#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
12436#define TIM_CCMR1_OC2FE_Pos (10U)
12437#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
12438#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
12439#define TIM_CCMR1_OC2PE_Pos (11U)
12440#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
12441#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
12443#define TIM_CCMR1_OC2M_Pos (12U)
12444#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
12445#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
12446#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
12447#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
12448#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
12449#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
12451#define TIM_CCMR1_OC2CE_Pos (15U)
12452#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
12453#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
12455/*----------------------------------------------------------------------------*/
12456
12457#define TIM_CCMR1_IC1PSC_Pos (2U)
12458#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
12459#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
12460#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
12461#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
12463#define TIM_CCMR1_IC1F_Pos (4U)
12464#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
12465#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
12466#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
12467#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
12468#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
12469#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
12471#define TIM_CCMR1_IC2PSC_Pos (10U)
12472#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
12473#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
12474#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
12475#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
12477#define TIM_CCMR1_IC2F_Pos (12U)
12478#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
12479#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
12480#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
12481#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
12482#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
12483#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
12485/****************** Bit definition for TIM_CCMR2 register *******************/
12486#define TIM_CCMR2_CC3S_Pos (0U)
12487#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
12488#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
12489#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
12490#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
12492#define TIM_CCMR2_OC3FE_Pos (2U)
12493#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
12494#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
12495#define TIM_CCMR2_OC3PE_Pos (3U)
12496#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
12497#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
12499#define TIM_CCMR2_OC3M_Pos (4U)
12500#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
12501#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
12502#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos)
12503#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos)
12504#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos)
12505#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
12509#define TIM_CCMR2_OC3CE_Pos (7U)
12510#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
12511#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
12513#define TIM_CCMR2_CC4S_Pos (8U)
12514#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
12515#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
12516#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
12517#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
12519#define TIM_CCMR2_OC4FE_Pos (10U)
12520#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
12521#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
12522#define TIM_CCMR2_OC4PE_Pos (11U)
12523#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
12524#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
12526#define TIM_CCMR2_OC4M_Pos (12U)
12527#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
12528#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
12529#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos)
12530#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos)
12531#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos)
12532#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
12534#define TIM_CCMR2_OC4CE_Pos (15U)
12535#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
12536#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
12538/*----------------------------------------------------------------------------*/
12539
12540#define TIM_CCMR2_IC3PSC_Pos (2U)
12541#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
12542#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
12543#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
12544#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
12546#define TIM_CCMR2_IC3F_Pos (4U)
12547#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
12548#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
12549#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
12550#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
12551#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
12552#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
12554#define TIM_CCMR2_IC4PSC_Pos (10U)
12555#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
12556#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
12557#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
12558#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
12560#define TIM_CCMR2_IC4F_Pos (12U)
12561#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
12562#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
12563#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
12564#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
12565#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
12566#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
12568/******************* Bit definition for TIM_CCER register *******************/
12569#define TIM_CCER_CC1E_Pos (0U)
12570#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
12571#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
12572#define TIM_CCER_CC1P_Pos (1U)
12573#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
12574#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
12575#define TIM_CCER_CC1NE_Pos (2U)
12576#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
12577#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
12578#define TIM_CCER_CC1NP_Pos (3U)
12579#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
12580#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
12581#define TIM_CCER_CC2E_Pos (4U)
12582#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
12583#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
12584#define TIM_CCER_CC2P_Pos (5U)
12585#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
12586#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
12587#define TIM_CCER_CC2NE_Pos (6U)
12588#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
12589#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
12590#define TIM_CCER_CC2NP_Pos (7U)
12591#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
12592#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
12593#define TIM_CCER_CC3E_Pos (8U)
12594#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
12595#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
12596#define TIM_CCER_CC3P_Pos (9U)
12597#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
12598#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
12599#define TIM_CCER_CC3NE_Pos (10U)
12600#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
12601#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
12602#define TIM_CCER_CC3NP_Pos (11U)
12603#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
12604#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
12605#define TIM_CCER_CC4E_Pos (12U)
12606#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
12607#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
12608#define TIM_CCER_CC4P_Pos (13U)
12609#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
12610#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
12611#define TIM_CCER_CC4NP_Pos (15U)
12612#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
12613#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
12614#define TIM_CCER_CC5E_Pos (16U)
12615#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
12616#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
12617#define TIM_CCER_CC5P_Pos (17U)
12618#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
12619#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
12620#define TIM_CCER_CC6E_Pos (20U)
12621#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
12622#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
12623#define TIM_CCER_CC6P_Pos (21U)
12624#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
12625#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
12628/******************* Bit definition for TIM_CNT register ********************/
12629#define TIM_CNT_CNT_Pos (0U)
12630#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
12631#define TIM_CNT_CNT TIM_CNT_CNT_Msk
12632#define TIM_CNT_UIFCPY_Pos (31U)
12633#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
12634#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
12636/******************* Bit definition for TIM_PSC register ********************/
12637#define TIM_PSC_PSC_Pos (0U)
12638#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
12639#define TIM_PSC_PSC TIM_PSC_PSC_Msk
12641/******************* Bit definition for TIM_ARR register ********************/
12642#define TIM_ARR_ARR_Pos (0U)
12643#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
12644#define TIM_ARR_ARR TIM_ARR_ARR_Msk
12646/******************* Bit definition for TIM_RCR register ********************/
12647#define TIM_RCR_REP_Pos (0U)
12648#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos)
12649#define TIM_RCR_REP TIM_RCR_REP_Msk
12651/******************* Bit definition for TIM_CCR1 register *******************/
12652#define TIM_CCR1_CCR1_Pos (0U)
12653#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
12654#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
12656/******************* Bit definition for TIM_CCR2 register *******************/
12657#define TIM_CCR2_CCR2_Pos (0U)
12658#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
12659#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
12661/******************* Bit definition for TIM_CCR3 register *******************/
12662#define TIM_CCR3_CCR3_Pos (0U)
12663#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
12664#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
12666/******************* Bit definition for TIM_CCR4 register *******************/
12667#define TIM_CCR4_CCR4_Pos (0U)
12668#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
12669#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
12671/******************* Bit definition for TIM_BDTR register *******************/
12672#define TIM_BDTR_DTG_Pos (0U)
12673#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
12674#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
12675#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
12676#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
12677#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
12678#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
12679#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
12680#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
12681#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
12682#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
12684#define TIM_BDTR_LOCK_Pos (8U)
12685#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
12686#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
12687#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
12688#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
12690#define TIM_BDTR_OSSI_Pos (10U)
12691#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
12692#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
12693#define TIM_BDTR_OSSR_Pos (11U)
12694#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
12695#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
12696#define TIM_BDTR_BKE_Pos (12U)
12697#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
12698#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
12699#define TIM_BDTR_BKP_Pos (13U)
12700#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
12701#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
12702#define TIM_BDTR_AOE_Pos (14U)
12703#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
12704#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
12705#define TIM_BDTR_MOE_Pos (15U)
12706#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
12707#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
12708#define TIM_BDTR_BKF_Pos (16U)
12709#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
12710#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
12711#define TIM_BDTR_BK2F_Pos (20U)
12712#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
12713#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
12714#define TIM_BDTR_BK2E_Pos (24U)
12715#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
12716#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
12717#define TIM_BDTR_BK2P_Pos (25U)
12718#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
12719#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
12721/******************* Bit definition for TIM_DCR register ********************/
12722#define TIM_DCR_DBA_Pos (0U)
12723#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
12724#define TIM_DCR_DBA TIM_DCR_DBA_Msk
12725#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
12726#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
12727#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
12728#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
12729#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
12731#define TIM_DCR_DBL_Pos (8U)
12732#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
12733#define TIM_DCR_DBL TIM_DCR_DBL_Msk
12734#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
12735#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
12736#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
12737#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
12738#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
12740/******************* Bit definition for TIM_DMAR register *******************/
12741#define TIM_DMAR_DMAB_Pos (0U)
12742#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
12743#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
12745/******************* Bit definition for TIM_OR regiter *********************/
12746#define TIM_OR_TI4_RMP_Pos (6U)
12747#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos)
12748#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk
12749#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos)
12750#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos)
12751#define TIM_OR_ITR1_RMP_Pos (10U)
12752#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos)
12753#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk
12754#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos)
12755#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos)
12757/******************* Bit definition for TIM2_OR register *******************/
12758#define TIM2_OR_ITR1_RMP_Pos (10U)
12759#define TIM2_OR_ITR1_RMP_Msk (0x3UL << TIM2_OR_ITR1_RMP_Pos)
12760#define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk
12761#define TIM2_OR_ITR1_RMP_0 (0x1UL << TIM2_OR_ITR1_RMP_Pos)
12762#define TIM2_OR_ITR1_RMP_1 (0x2UL << TIM2_OR_ITR1_RMP_Pos)
12764/******************* Bit definition for TIM5_OR register *******************/
12765#define TIM5_OR_TI4_RMP_Pos (6U)
12766#define TIM5_OR_TI4_RMP_Msk (0x3UL << TIM5_OR_TI4_RMP_Pos)
12767#define TIM5_OR_TI4_RMP TIM5_OR_TI4_RMP_Msk
12768#define TIM5_OR_TI4_RMP_0 (0x1UL << TIM5_OR_TI4_RMP_Pos)
12769#define TIM5_OR_TI4_RMP_1 (0x2UL << TIM5_OR_TI4_RMP_Pos)
12771/******************* Bit definition for TIM11_OR register *******************/
12772#define TIM11_OR_TI1_RMP_Pos (0U)
12773#define TIM11_OR_TI1_RMP_Msk (0x3UL << TIM11_OR_TI1_RMP_Pos)
12774#define TIM11_OR_TI1_RMP TIM11_OR_TI1_RMP_Msk
12775#define TIM11_OR_TI1_RMP_0 (0x1UL << TIM11_OR_TI1_RMP_Pos)
12776#define TIM11_OR_TI1_RMP_1 (0x2UL << TIM11_OR_TI1_RMP_Pos)
12778/****************** Bit definition for TIM_CCMR3 register *******************/
12779#define TIM_CCMR3_OC5FE_Pos (2U)
12780#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
12781#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
12782#define TIM_CCMR3_OC5PE_Pos (3U)
12783#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
12784#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
12786#define TIM_CCMR3_OC5M_Pos (4U)
12787#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
12788#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
12789#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos)
12790#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos)
12791#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos)
12792#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
12794#define TIM_CCMR3_OC5CE_Pos (7U)
12795#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
12796#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
12798#define TIM_CCMR3_OC6FE_Pos (10U)
12799#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
12800#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
12801#define TIM_CCMR3_OC6PE_Pos (11U)
12802#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
12803#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
12805#define TIM_CCMR3_OC6M_Pos (12U)
12806#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
12807#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
12808#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos)
12809#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos)
12810#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos)
12811#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
12813#define TIM_CCMR3_OC6CE_Pos (15U)
12814#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
12815#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
12817/******************* Bit definition for TIM_CCR5 register *******************/
12818#define TIM_CCR5_CCR5_Pos (0U)
12819#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
12820#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
12821#define TIM_CCR5_GC5C1_Pos (29U)
12822#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
12823#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
12824#define TIM_CCR5_GC5C2_Pos (30U)
12825#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
12826#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
12827#define TIM_CCR5_GC5C3_Pos (31U)
12828#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
12829#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
12831/******************* Bit definition for TIM_CCR6 register *******************/
12832#define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU)
12835/******************************************************************************/
12836/* */
12837/* Low Power Timer (LPTIM) */
12838/* */
12839/******************************************************************************/
12840/****************** Bit definition for LPTIM_ISR register *******************/
12841#define LPTIM_ISR_CMPM_Pos (0U)
12842#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
12843#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
12844#define LPTIM_ISR_ARRM_Pos (1U)
12845#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
12846#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
12847#define LPTIM_ISR_EXTTRIG_Pos (2U)
12848#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
12849#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
12850#define LPTIM_ISR_CMPOK_Pos (3U)
12851#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
12852#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
12853#define LPTIM_ISR_ARROK_Pos (4U)
12854#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
12855#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
12856#define LPTIM_ISR_UP_Pos (5U)
12857#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
12858#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
12859#define LPTIM_ISR_DOWN_Pos (6U)
12860#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
12861#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
12863/****************** Bit definition for LPTIM_ICR register *******************/
12864#define LPTIM_ICR_CMPMCF_Pos (0U)
12865#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
12866#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
12867#define LPTIM_ICR_ARRMCF_Pos (1U)
12868#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
12869#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
12870#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
12871#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
12872#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
12873#define LPTIM_ICR_CMPOKCF_Pos (3U)
12874#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
12875#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
12876#define LPTIM_ICR_ARROKCF_Pos (4U)
12877#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
12878#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
12879#define LPTIM_ICR_UPCF_Pos (5U)
12880#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
12881#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
12882#define LPTIM_ICR_DOWNCF_Pos (6U)
12883#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
12884#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
12886/****************** Bit definition for LPTIM_IER register *******************/
12887#define LPTIM_IER_CMPMIE_Pos (0U)
12888#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
12889#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
12890#define LPTIM_IER_ARRMIE_Pos (1U)
12891#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
12892#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
12893#define LPTIM_IER_EXTTRIGIE_Pos (2U)
12894#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
12895#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
12896#define LPTIM_IER_CMPOKIE_Pos (3U)
12897#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
12898#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
12899#define LPTIM_IER_ARROKIE_Pos (4U)
12900#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
12901#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
12902#define LPTIM_IER_UPIE_Pos (5U)
12903#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
12904#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
12905#define LPTIM_IER_DOWNIE_Pos (6U)
12906#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
12907#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
12909/****************** Bit definition for LPTIM_CFGR register*******************/
12910#define LPTIM_CFGR_CKSEL_Pos (0U)
12911#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
12912#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
12914#define LPTIM_CFGR_CKPOL_Pos (1U)
12915#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
12916#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
12917#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
12918#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
12920#define LPTIM_CFGR_CKFLT_Pos (3U)
12921#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
12922#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
12923#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
12924#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
12926#define LPTIM_CFGR_TRGFLT_Pos (6U)
12927#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
12928#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
12929#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
12930#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
12932#define LPTIM_CFGR_PRESC_Pos (9U)
12933#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
12934#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
12935#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
12936#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
12937#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
12939#define LPTIM_CFGR_TRIGSEL_Pos (13U)
12940#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
12941#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
12942#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
12943#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
12944#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
12946#define LPTIM_CFGR_TRIGEN_Pos (17U)
12947#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
12948#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
12949#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
12950#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
12952#define LPTIM_CFGR_TIMOUT_Pos (19U)
12953#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
12954#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
12955#define LPTIM_CFGR_WAVE_Pos (20U)
12956#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
12957#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
12958#define LPTIM_CFGR_WAVPOL_Pos (21U)
12959#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
12960#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
12961#define LPTIM_CFGR_PRELOAD_Pos (22U)
12962#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
12963#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
12964#define LPTIM_CFGR_COUNTMODE_Pos (23U)
12965#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
12966#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
12967#define LPTIM_CFGR_ENC_Pos (24U)
12968#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
12969#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
12971/****************** Bit definition for LPTIM_CR register ********************/
12972#define LPTIM_CR_ENABLE_Pos (0U)
12973#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
12974#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
12975#define LPTIM_CR_SNGSTRT_Pos (1U)
12976#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos)
12977#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
12978#define LPTIM_CR_CNTSTRT_Pos (2U)
12979#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
12980#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
12982/****************** Bit definition for LPTIM_CMP register *******************/
12983#define LPTIM_CMP_CMP_Pos (0U)
12984#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
12985#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
12987/****************** Bit definition for LPTIM_ARR register *******************/
12988#define LPTIM_ARR_ARR_Pos (0U)
12989#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
12990#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
12992/****************** Bit definition for LPTIM_CNT register *******************/
12993#define LPTIM_CNT_CNT_Pos (0U)
12994#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
12995#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
12996/******************************************************************************/
12997/* */
12998/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
12999/* */
13000/******************************************************************************/
13001/*
13002 * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)
13003 */
13004/* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */
13005#define USART_TCBGT_SUPPORT
13006/****************** Bit definition for USART_CR1 register *******************/
13007#define USART_CR1_UE_Pos (0U)
13008#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
13009#define USART_CR1_UE USART_CR1_UE_Msk
13010#define USART_CR1_RE_Pos (2U)
13011#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
13012#define USART_CR1_RE USART_CR1_RE_Msk
13013#define USART_CR1_TE_Pos (3U)
13014#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
13015#define USART_CR1_TE USART_CR1_TE_Msk
13016#define USART_CR1_IDLEIE_Pos (4U)
13017#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
13018#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
13019#define USART_CR1_RXNEIE_Pos (5U)
13020#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
13021#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
13022#define USART_CR1_TCIE_Pos (6U)
13023#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
13024#define USART_CR1_TCIE USART_CR1_TCIE_Msk
13025#define USART_CR1_TXEIE_Pos (7U)
13026#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
13027#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
13028#define USART_CR1_PEIE_Pos (8U)
13029#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
13030#define USART_CR1_PEIE USART_CR1_PEIE_Msk
13031#define USART_CR1_PS_Pos (9U)
13032#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
13033#define USART_CR1_PS USART_CR1_PS_Msk
13034#define USART_CR1_PCE_Pos (10U)
13035#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
13036#define USART_CR1_PCE USART_CR1_PCE_Msk
13037#define USART_CR1_WAKE_Pos (11U)
13038#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
13039#define USART_CR1_WAKE USART_CR1_WAKE_Msk
13040#define USART_CR1_M_Pos (12U)
13041#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
13042#define USART_CR1_M USART_CR1_M_Msk
13043#define USART_CR1_M0 (0x00001UL << USART_CR1_M_Pos)
13044#define USART_CR1_MME_Pos (13U)
13045#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
13046#define USART_CR1_MME USART_CR1_MME_Msk
13047#define USART_CR1_CMIE_Pos (14U)
13048#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
13049#define USART_CR1_CMIE USART_CR1_CMIE_Msk
13050#define USART_CR1_OVER8_Pos (15U)
13051#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
13052#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
13053#define USART_CR1_DEDT_Pos (16U)
13054#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
13055#define USART_CR1_DEDT USART_CR1_DEDT_Msk
13056#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
13057#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
13058#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
13059#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
13060#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
13061#define USART_CR1_DEAT_Pos (21U)
13062#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
13063#define USART_CR1_DEAT USART_CR1_DEAT_Msk
13064#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
13065#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
13066#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
13067#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
13068#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
13069#define USART_CR1_RTOIE_Pos (26U)
13070#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
13071#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
13072#define USART_CR1_EOBIE_Pos (27U)
13073#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
13074#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
13075#define USART_CR1_M1 0x10000000U
13077/* Legacy defines */
13078#define USART_CR1_M_0 USART_CR1_M0
13079#define USART_CR1_M_1 USART_CR1_M1
13081/****************** Bit definition for USART_CR2 register *******************/
13082#define USART_CR2_ADDM7_Pos (4U)
13083#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
13084#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
13085#define USART_CR2_LBDL_Pos (5U)
13086#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
13087#define USART_CR2_LBDL USART_CR2_LBDL_Msk
13088#define USART_CR2_LBDIE_Pos (6U)
13089#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
13090#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
13091#define USART_CR2_LBCL_Pos (8U)
13092#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
13093#define USART_CR2_LBCL USART_CR2_LBCL_Msk
13094#define USART_CR2_CPHA_Pos (9U)
13095#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
13096#define USART_CR2_CPHA USART_CR2_CPHA_Msk
13097#define USART_CR2_CPOL_Pos (10U)
13098#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
13099#define USART_CR2_CPOL USART_CR2_CPOL_Msk
13100#define USART_CR2_CLKEN_Pos (11U)
13101#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
13102#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
13103#define USART_CR2_STOP_Pos (12U)
13104#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
13105#define USART_CR2_STOP USART_CR2_STOP_Msk
13106#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
13107#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
13108#define USART_CR2_LINEN_Pos (14U)
13109#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
13110#define USART_CR2_LINEN USART_CR2_LINEN_Msk
13111#define USART_CR2_SWAP_Pos (15U)
13112#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
13113#define USART_CR2_SWAP USART_CR2_SWAP_Msk
13114#define USART_CR2_RXINV_Pos (16U)
13115#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
13116#define USART_CR2_RXINV USART_CR2_RXINV_Msk
13117#define USART_CR2_TXINV_Pos (17U)
13118#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
13119#define USART_CR2_TXINV USART_CR2_TXINV_Msk
13120#define USART_CR2_DATAINV_Pos (18U)
13121#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
13122#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
13123#define USART_CR2_MSBFIRST_Pos (19U)
13124#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
13125#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
13126#define USART_CR2_ABREN_Pos (20U)
13127#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
13128#define USART_CR2_ABREN USART_CR2_ABREN_Msk
13129#define USART_CR2_ABRMODE_Pos (21U)
13130#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
13131#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
13132#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
13133#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
13134#define USART_CR2_RTOEN_Pos (23U)
13135#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
13136#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
13137#define USART_CR2_ADD_Pos (24U)
13138#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
13139#define USART_CR2_ADD USART_CR2_ADD_Msk
13141/****************** Bit definition for USART_CR3 register *******************/
13142#define USART_CR3_EIE_Pos (0U)
13143#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
13144#define USART_CR3_EIE USART_CR3_EIE_Msk
13145#define USART_CR3_IREN_Pos (1U)
13146#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
13147#define USART_CR3_IREN USART_CR3_IREN_Msk
13148#define USART_CR3_IRLP_Pos (2U)
13149#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
13150#define USART_CR3_IRLP USART_CR3_IRLP_Msk
13151#define USART_CR3_HDSEL_Pos (3U)
13152#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
13153#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
13154#define USART_CR3_NACK_Pos (4U)
13155#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
13156#define USART_CR3_NACK USART_CR3_NACK_Msk
13157#define USART_CR3_SCEN_Pos (5U)
13158#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
13159#define USART_CR3_SCEN USART_CR3_SCEN_Msk
13160#define USART_CR3_DMAR_Pos (6U)
13161#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
13162#define USART_CR3_DMAR USART_CR3_DMAR_Msk
13163#define USART_CR3_DMAT_Pos (7U)
13164#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
13165#define USART_CR3_DMAT USART_CR3_DMAT_Msk
13166#define USART_CR3_RTSE_Pos (8U)
13167#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
13168#define USART_CR3_RTSE USART_CR3_RTSE_Msk
13169#define USART_CR3_CTSE_Pos (9U)
13170#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
13171#define USART_CR3_CTSE USART_CR3_CTSE_Msk
13172#define USART_CR3_CTSIE_Pos (10U)
13173#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
13174#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
13175#define USART_CR3_ONEBIT_Pos (11U)
13176#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
13177#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
13178#define USART_CR3_OVRDIS_Pos (12U)
13179#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
13180#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
13181#define USART_CR3_DDRE_Pos (13U)
13182#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
13183#define USART_CR3_DDRE USART_CR3_DDRE_Msk
13184#define USART_CR3_DEM_Pos (14U)
13185#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
13186#define USART_CR3_DEM USART_CR3_DEM_Msk
13187#define USART_CR3_DEP_Pos (15U)
13188#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
13189#define USART_CR3_DEP USART_CR3_DEP_Msk
13190#define USART_CR3_SCARCNT_Pos (17U)
13191#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
13192#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
13193#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
13194#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
13195#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
13196#define USART_CR3_TCBGTIE_Pos (24U)
13197#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)
13198#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk
13200/****************** Bit definition for USART_BRR register *******************/
13201#define USART_BRR_DIV_FRACTION_Pos (0U)
13202#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
13203#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
13204#define USART_BRR_DIV_MANTISSA_Pos (4U)
13205#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
13206#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
13208/****************** Bit definition for USART_GTPR register ******************/
13209#define USART_GTPR_PSC_Pos (0U)
13210#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
13211#define USART_GTPR_PSC USART_GTPR_PSC_Msk
13212#define USART_GTPR_GT_Pos (8U)
13213#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
13214#define USART_GTPR_GT USART_GTPR_GT_Msk
13217/******************* Bit definition for USART_RTOR register *****************/
13218#define USART_RTOR_RTO_Pos (0U)
13219#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
13220#define USART_RTOR_RTO USART_RTOR_RTO_Msk
13221#define USART_RTOR_BLEN_Pos (24U)
13222#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
13223#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
13225/******************* Bit definition for USART_RQR register ******************/
13226#define USART_RQR_ABRRQ_Pos (0U)
13227#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
13228#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
13229#define USART_RQR_SBKRQ_Pos (1U)
13230#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
13231#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
13232#define USART_RQR_MMRQ_Pos (2U)
13233#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
13234#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
13235#define USART_RQR_RXFRQ_Pos (3U)
13236#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
13237#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
13238#define USART_RQR_TXFRQ_Pos (4U)
13239#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
13240#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
13242/******************* Bit definition for USART_ISR register ******************/
13243#define USART_ISR_PE_Pos (0U)
13244#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
13245#define USART_ISR_PE USART_ISR_PE_Msk
13246#define USART_ISR_FE_Pos (1U)
13247#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
13248#define USART_ISR_FE USART_ISR_FE_Msk
13249#define USART_ISR_NE_Pos (2U)
13250#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
13251#define USART_ISR_NE USART_ISR_NE_Msk
13252#define USART_ISR_ORE_Pos (3U)
13253#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
13254#define USART_ISR_ORE USART_ISR_ORE_Msk
13255#define USART_ISR_IDLE_Pos (4U)
13256#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
13257#define USART_ISR_IDLE USART_ISR_IDLE_Msk
13258#define USART_ISR_RXNE_Pos (5U)
13259#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos)
13260#define USART_ISR_RXNE USART_ISR_RXNE_Msk
13261#define USART_ISR_TC_Pos (6U)
13262#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
13263#define USART_ISR_TC USART_ISR_TC_Msk
13264#define USART_ISR_TXE_Pos (7U)
13265#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos)
13266#define USART_ISR_TXE USART_ISR_TXE_Msk
13267#define USART_ISR_LBDF_Pos (8U)
13268#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
13269#define USART_ISR_LBDF USART_ISR_LBDF_Msk
13270#define USART_ISR_CTSIF_Pos (9U)
13271#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
13272#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
13273#define USART_ISR_CTS_Pos (10U)
13274#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
13275#define USART_ISR_CTS USART_ISR_CTS_Msk
13276#define USART_ISR_RTOF_Pos (11U)
13277#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
13278#define USART_ISR_RTOF USART_ISR_RTOF_Msk
13279#define USART_ISR_EOBF_Pos (12U)
13280#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
13281#define USART_ISR_EOBF USART_ISR_EOBF_Msk
13282#define USART_ISR_ABRE_Pos (14U)
13283#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
13284#define USART_ISR_ABRE USART_ISR_ABRE_Msk
13285#define USART_ISR_ABRF_Pos (15U)
13286#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
13287#define USART_ISR_ABRF USART_ISR_ABRF_Msk
13288#define USART_ISR_BUSY_Pos (16U)
13289#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
13290#define USART_ISR_BUSY USART_ISR_BUSY_Msk
13291#define USART_ISR_CMF_Pos (17U)
13292#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
13293#define USART_ISR_CMF USART_ISR_CMF_Msk
13294#define USART_ISR_SBKF_Pos (18U)
13295#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
13296#define USART_ISR_SBKF USART_ISR_SBKF_Msk
13297#define USART_ISR_RWU_Pos (19U)
13298#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
13299#define USART_ISR_RWU USART_ISR_RWU_Msk
13300#define USART_ISR_TEACK_Pos (21U)
13301#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
13302#define USART_ISR_TEACK USART_ISR_TEACK_Msk
13303#define USART_ISR_TCBGT_Pos (25U)
13304#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)
13305#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk
13307/******************* Bit definition for USART_ICR register ******************/
13308#define USART_ICR_PECF_Pos (0U)
13309#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
13310#define USART_ICR_PECF USART_ICR_PECF_Msk
13311#define USART_ICR_FECF_Pos (1U)
13312#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
13313#define USART_ICR_FECF USART_ICR_FECF_Msk
13314#define USART_ICR_NCF_Pos (2U)
13315#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos)
13316#define USART_ICR_NCF USART_ICR_NCF_Msk
13317#define USART_ICR_ORECF_Pos (3U)
13318#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
13319#define USART_ICR_ORECF USART_ICR_ORECF_Msk
13320#define USART_ICR_IDLECF_Pos (4U)
13321#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
13322#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
13323#define USART_ICR_TCCF_Pos (6U)
13324#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
13325#define USART_ICR_TCCF USART_ICR_TCCF_Msk
13326#define USART_ICR_TCBGTCF_Pos (7U)
13327#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)
13328#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk
13329#define USART_ICR_LBDCF_Pos (8U)
13330#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
13331#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
13332#define USART_ICR_CTSCF_Pos (9U)
13333#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
13334#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
13335#define USART_ICR_RTOCF_Pos (11U)
13336#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
13337#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
13338#define USART_ICR_EOBCF_Pos (12U)
13339#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
13340#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
13341#define USART_ICR_CMCF_Pos (17U)
13342#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
13343#define USART_ICR_CMCF USART_ICR_CMCF_Msk
13345/******************* Bit definition for USART_RDR register ******************/
13346#define USART_RDR_RDR_Pos (0U)
13347#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
13348#define USART_RDR_RDR USART_RDR_RDR_Msk
13350/******************* Bit definition for USART_TDR register ******************/
13351#define USART_TDR_TDR_Pos (0U)
13352#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
13353#define USART_TDR_TDR USART_TDR_TDR_Msk
13355/******************************************************************************/
13356/* */
13357/* Window WATCHDOG */
13358/* */
13359/******************************************************************************/
13360/******************* Bit definition for WWDG_CR register ********************/
13361#define WWDG_CR_T_Pos (0U)
13362#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
13363#define WWDG_CR_T WWDG_CR_T_Msk
13364#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
13365#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
13366#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
13367#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
13368#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
13369#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
13370#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
13373#define WWDG_CR_WDGA_Pos (7U)
13374#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
13375#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
13377/******************* Bit definition for WWDG_CFR register *******************/
13378#define WWDG_CFR_W_Pos (0U)
13379#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
13380#define WWDG_CFR_W WWDG_CFR_W_Msk
13381#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
13382#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
13383#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
13384#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
13385#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
13386#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
13387#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
13390#define WWDG_CFR_WDGTB_Pos (7U)
13391#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
13392#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
13393#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
13394#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
13397#define WWDG_CFR_EWI_Pos (9U)
13398#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
13399#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
13401/******************* Bit definition for WWDG_SR register ********************/
13402#define WWDG_SR_EWIF_Pos (0U)
13403#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
13404#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
13406/******************************************************************************/
13407/* */
13408/* DBG */
13409/* */
13410/******************************************************************************/
13411/******************** Bit definition for DBGMCU_IDCODE register *************/
13412#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
13413#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
13414#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
13415#define DBGMCU_IDCODE_REV_ID_Pos (16U)
13416#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
13417#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
13418
13419/******************** Bit definition for DBGMCU_CR register *****************/
13420#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
13421#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
13422#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
13423#define DBGMCU_CR_DBG_STOP_Pos (1U)
13424#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
13425#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
13426#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
13427#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
13428#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
13429#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
13430#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
13431#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
13432
13433#define DBGMCU_CR_TRACE_MODE_Pos (6U)
13434#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
13435#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
13436#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
13437#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
13439/******************** Bit definition for DBGMCU_APB1_FZ register ************/
13440#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
13441#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
13442#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
13443#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
13444#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
13445#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
13446#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
13447#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
13448#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
13449#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
13450#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
13451#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
13452#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
13453#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
13454#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
13455#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
13456#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
13457#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
13458#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
13459#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos)
13460#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
13461#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
13462#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos)
13463#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
13464#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
13465#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos)
13466#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
13467#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U)
13468#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos)
13469#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk
13470#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
13471#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
13472#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
13473#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
13474#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
13475#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
13476#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
13477#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
13478#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
13479#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
13480#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
13481#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
13482#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
13483#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
13484#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
13485#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
13486#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos)
13487#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
13488#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
13489#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos)
13490#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
13491
13492/******************** Bit definition for DBGMCU_APB2_FZ register ************/
13493#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
13494#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos)
13495#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
13496#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
13497#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos)
13498#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
13499#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
13500#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
13501#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
13502#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
13503#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
13504#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
13505#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
13506#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
13507#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
13508
13509
13510/******************************************************************************/
13511/* */
13512/* USB_OTG */
13513/* */
13514/******************************************************************************/
13515/******************** Bit definition for USB_OTG_GOTGCTL register ********************/
13516#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
13517#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
13518#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
13519#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
13520#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
13521#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
13522#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
13523#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
13524#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
13525#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
13526#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
13527#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
13528#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
13529#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
13530#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
13531#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
13532#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
13533#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
13534#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
13535#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
13536#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
13537#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
13538#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
13539#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
13540#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
13541#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
13542#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
13543#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
13544#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
13545#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
13546#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
13547#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
13548#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
13549#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
13550#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
13551#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
13552#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
13553#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
13554#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
13555#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
13556#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
13557#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
13558#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
13559#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
13560#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
13561#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
13562#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
13563#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
13564#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
13565#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
13566#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
13567#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
13568#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
13569#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
13571/******************** Bit definition for USB_OTG_HCFG register ********************/
13572#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
13573#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
13574#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
13575#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
13576#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
13577#define USB_OTG_HCFG_FSLSS_Pos (2U)
13578#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
13579#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
13581/******************** Bit definition for USB_OTG_DCFG register ********************/
13582#define USB_OTG_DCFG_DSPD_Pos (0U)
13583#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
13584#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
13585#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
13586#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
13587#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
13588#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
13589#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
13591#define USB_OTG_DCFG_DAD_Pos (4U)
13592#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
13593#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
13594#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
13595#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
13596#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
13597#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
13598#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
13599#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
13600#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
13602#define USB_OTG_DCFG_PFIVL_Pos (11U)
13603#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
13604#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
13605#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
13606#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
13608#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
13609#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13610#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
13611#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13612#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
13614/******************** Bit definition for USB_OTG_PCGCR register ********************/
13615#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
13616#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
13617#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
13618#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
13619#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
13620#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
13621#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
13622#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
13623#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
13625/******************** Bit definition for USB_OTG_GOTGINT register ********************/
13626#define USB_OTG_GOTGINT_SEDET_Pos (2U)
13627#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
13628#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
13629#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
13630#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
13631#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
13632#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
13633#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
13634#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
13635#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
13636#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
13637#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
13638#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
13639#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
13640#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
13641#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
13642#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
13643#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
13644#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
13645#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos)
13646#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk
13648/******************** Bit definition for USB_OTG_DCTL register ********************/
13649#define USB_OTG_DCTL_RWUSIG_Pos (0U)
13650#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
13651#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
13652#define USB_OTG_DCTL_SDIS_Pos (1U)
13653#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
13654#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
13655#define USB_OTG_DCTL_GINSTS_Pos (2U)
13656#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
13657#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
13658#define USB_OTG_DCTL_GONSTS_Pos (3U)
13659#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
13660#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
13662#define USB_OTG_DCTL_TCTL_Pos (4U)
13663#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
13664#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
13665#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
13666#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
13667#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
13668#define USB_OTG_DCTL_SGINAK_Pos (7U)
13669#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
13670#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
13671#define USB_OTG_DCTL_CGINAK_Pos (8U)
13672#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
13673#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
13674#define USB_OTG_DCTL_SGONAK_Pos (9U)
13675#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
13676#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
13677#define USB_OTG_DCTL_CGONAK_Pos (10U)
13678#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
13679#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
13680#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
13681#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
13682#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
13684/******************** Bit definition for USB_OTG_HFIR register ********************/
13685#define USB_OTG_HFIR_FRIVL_Pos (0U)
13686#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
13687#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
13689/******************** Bit definition for USB_OTG_HFNUM register ********************/
13690#define USB_OTG_HFNUM_FRNUM_Pos (0U)
13691#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
13692#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
13693#define USB_OTG_HFNUM_FTREM_Pos (16U)
13694#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
13695#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
13697/******************** Bit definition for USB_OTG_DSTS register ********************/
13698#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
13699#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
13700#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
13702#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
13703#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
13704#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
13705#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
13706#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
13707#define USB_OTG_DSTS_EERR_Pos (3U)
13708#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
13709#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
13710#define USB_OTG_DSTS_FNSOF_Pos (8U)
13711#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
13712#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
13714/******************** Bit definition for USB_OTG_GAHBCFG register ********************/
13715#define USB_OTG_GAHBCFG_GINT_Pos (0U)
13716#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
13717#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
13718#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
13719#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13720#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
13721#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13722#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13723#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13724#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13725#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
13726#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
13727#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
13728#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
13729#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
13730#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
13731#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
13732#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
13733#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
13734#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
13736/******************** Bit definition for USB_OTG_GUSBCFG register ********************/
13737#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
13738#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13739#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
13740#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13741#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13742#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
13743#define USB_OTG_GUSBCFG_PHYIF_Pos (3U)
13744#define USB_OTG_GUSBCFG_PHYIF_Msk (0x1UL << USB_OTG_GUSBCFG_PHYIF_Pos)
13745#define USB_OTG_GUSBCFG_PHYIF USB_OTG_GUSBCFG_PHYIF_Msk
13746#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos (4U)
13747#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos)
13748#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk
13749#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
13750#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
13751#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
13752#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
13753#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
13754#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
13755#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
13756#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
13757#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
13758#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
13759#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
13760#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
13761#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
13762#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
13763#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
13764#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
13765#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
13766#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
13767#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
13768#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
13769#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
13770#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
13771#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
13772#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
13773#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
13774#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
13775#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
13776#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
13777#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
13778#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
13779#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
13780#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
13781#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
13782#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
13783#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
13784#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
13785#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
13786#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
13787#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
13788#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
13789#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
13790#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
13791#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
13792#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
13793#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
13794#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
13795#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
13796#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
13797#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
13798#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
13799#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
13800#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
13801#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
13802#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
13803#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
13805/******************** Bit definition for USB_OTG_GRSTCTL register ********************/
13806#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
13807#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
13808#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
13809#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
13810#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
13811#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
13812#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
13813#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
13814#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
13815#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
13816#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
13817#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
13818#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
13819#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
13820#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
13821#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
13822#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13823#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
13824#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13825#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13826#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13827#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13828#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
13829#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
13830#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
13831#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
13832#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
13833#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
13834#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
13836/******************** Bit definition for USB_OTG_DIEPMSK register ********************/
13837#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
13838#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
13839#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
13840#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
13841#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
13842#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
13843#define USB_OTG_DIEPMSK_TOM_Pos (3U)
13844#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
13845#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
13846#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
13847#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
13848#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
13849#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
13850#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
13851#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
13852#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
13853#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
13854#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
13855#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
13856#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
13857#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
13858#define USB_OTG_DIEPMSK_BIM_Pos (9U)
13859#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
13860#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
13862/******************** Bit definition for USB_OTG_HPTXSTS register ********************/
13863#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
13864#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
13865#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
13866#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
13867#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13868#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
13869#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13870#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13871#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13872#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13873#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13874#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13875#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13876#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
13878#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
13879#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13880#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
13881#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13882#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13883#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13884#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13885#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13886#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13887#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13888#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
13890/******************** Bit definition for USB_OTG_HAINT register ********************/
13891#define USB_OTG_HAINT_HAINT_Pos (0U)
13892#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
13893#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
13895/******************** Bit definition for USB_OTG_DOEPMSK register ********************/
13896#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
13897#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
13898#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
13899#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
13900#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
13901#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
13902#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
13903#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
13904#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
13905#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
13906#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
13907#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
13908#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
13909#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
13910#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
13911#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
13912#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
13913#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
13914#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
13915#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
13916#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
13917#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
13918#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
13919#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
13920#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
13921#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
13922#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
13923#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
13924#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
13925#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
13926#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
13927#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
13928#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
13929#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
13930#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
13931#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
13933/******************** Bit definition for USB_OTG_GINTSTS register ********************/
13934#define USB_OTG_GINTSTS_CMOD_Pos (0U)
13935#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
13936#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
13937#define USB_OTG_GINTSTS_MMIS_Pos (1U)
13938#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
13939#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
13940#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
13941#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
13942#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
13943#define USB_OTG_GINTSTS_SOF_Pos (3U)
13944#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
13945#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
13946#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
13947#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
13948#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
13949#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
13950#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
13951#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
13952#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
13953#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
13954#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
13955#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
13956#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
13957#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
13958#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
13959#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
13960#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
13961#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
13962#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
13963#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
13964#define USB_OTG_GINTSTS_USBRST_Pos (12U)
13965#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
13966#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
13967#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
13968#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
13969#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
13970#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
13971#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
13972#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
13973#define USB_OTG_GINTSTS_EOPF_Pos (15U)
13974#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
13975#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
13976#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
13977#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
13978#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
13979#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
13980#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
13981#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
13982#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
13983#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
13984#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
13985#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
13986#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
13987#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
13988#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
13989#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
13990#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
13991#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
13992#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
13993#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
13994#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
13995#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
13996#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
13997#define USB_OTG_GINTSTS_HCINT_Pos (25U)
13998#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
13999#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
14000#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
14001#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
14002#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
14003#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
14004#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
14005#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
14006#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
14007#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
14008#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
14009#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
14010#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
14011#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
14012#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
14013#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
14014#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
14015#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
14016#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
14017#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
14019/******************** Bit definition for USB_OTG_GINTMSK register ********************/
14020#define USB_OTG_GINTMSK_MMISM_Pos (1U)
14021#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
14022#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
14023#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
14024#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
14025#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
14026#define USB_OTG_GINTMSK_SOFM_Pos (3U)
14027#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
14028#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
14029#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
14030#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
14031#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
14032#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
14033#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
14034#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
14035#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
14036#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
14037#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
14038#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
14039#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
14040#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
14041#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
14042#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
14043#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
14044#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
14045#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
14046#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
14047#define USB_OTG_GINTMSK_USBRST_Pos (12U)
14048#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
14049#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
14050#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
14051#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
14052#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
14053#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
14054#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
14055#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
14056#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
14057#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
14058#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
14059#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
14060#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
14061#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
14062#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
14063#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
14064#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
14065#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
14066#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
14067#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
14068#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
14069#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
14070#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
14071#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
14072#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
14073#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
14074#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
14075#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
14076#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
14077#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
14078#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
14079#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
14080#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
14081#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
14082#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
14083#define USB_OTG_GINTMSK_HCIM_Pos (25U)
14084#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
14085#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
14086#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
14087#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
14088#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
14089#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
14090#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
14091#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
14092#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
14093#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
14094#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
14095#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
14096#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
14097#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
14098#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
14099#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
14100#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
14101#define USB_OTG_GINTMSK_WUIM_Pos (31U)
14102#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
14103#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
14105/******************** Bit definition for USB_OTG_DAINT register ********************/
14106#define USB_OTG_DAINT_IEPINT_Pos (0U)
14107#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
14108#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
14109#define USB_OTG_DAINT_OEPINT_Pos (16U)
14110#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
14111#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
14113/******************** Bit definition for USB_OTG_HAINTMSK register ********************/
14114#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
14115#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
14116#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
14118/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
14119#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
14120#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
14121#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
14122#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
14123#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
14124#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
14125#define USB_OTG_GRXSTSP_DPID_Pos (15U)
14126#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
14127#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
14128#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
14129#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
14130#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
14132/******************** Bit definition for USB_OTG_DAINTMSK register ********************/
14133#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
14134#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
14135#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
14136#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
14137#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
14138#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
14140/******************** Bit definition for OTG register ********************/
14141
14142#define USB_OTG_CHNUM_Pos (0U)
14143#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
14144#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
14145#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
14146#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
14147#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
14148#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
14149#define USB_OTG_BCNT_Pos (4U)
14150#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
14151#define USB_OTG_BCNT USB_OTG_BCNT_Msk
14153#define USB_OTG_DPID_Pos (15U)
14154#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
14155#define USB_OTG_DPID USB_OTG_DPID_Msk
14156#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
14157#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
14159#define USB_OTG_PKTSTS_Pos (17U)
14160#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
14161#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
14162#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
14163#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
14164#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
14165#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
14167#define USB_OTG_EPNUM_Pos (0U)
14168#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
14169#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
14170#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
14171#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
14172#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
14173#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
14175#define USB_OTG_FRMNUM_Pos (21U)
14176#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
14177#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
14178#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
14179#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
14180#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
14181#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
14183/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
14184#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
14185#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
14186#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
14188/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
14189#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
14190#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
14191#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
14193/******************** Bit definition for OTG register ********************/
14194#define USB_OTG_NPTXFSA_Pos (0U)
14195#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
14196#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
14197#define USB_OTG_NPTXFD_Pos (16U)
14198#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
14199#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
14200#define USB_OTG_TX0FSA_Pos (0U)
14201#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
14202#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
14203#define USB_OTG_TX0FD_Pos (16U)
14204#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
14205#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
14207/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
14208#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
14209#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
14210#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
14212/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
14213#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
14214#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
14215#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
14217#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
14218#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14219#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
14220#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14221#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14222#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14223#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14224#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14225#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14226#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14227#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
14229#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
14230#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14231#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
14232#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14233#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14234#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14235#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14236#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14237#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14238#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
14240/******************** Bit definition for USB_OTG_DTHRCTL register ********************/
14241#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
14242#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
14243#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
14244#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
14245#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
14246#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
14248#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
14249#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14250#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
14251#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14252#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14253#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14254#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14255#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14256#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14257#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14258#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14259#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
14260#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
14261#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
14262#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
14264#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
14265#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14266#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
14267#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14268#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14269#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14270#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14271#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14272#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14273#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14274#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14275#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
14276#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
14277#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
14278#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
14280/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
14281#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
14282#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
14283#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
14285/******************** Bit definition for USB_OTG_DEACHINT register ********************/
14286#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
14287#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
14288#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
14289#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
14290#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
14291#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
14293/******************** Bit definition for USB_OTG_GCCFG register ********************/
14294#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
14295#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
14296#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
14297#define USB_OTG_GCCFG_VBDEN_Pos (21U)
14298#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
14299#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
14301/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
14302#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
14303#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
14304#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
14305#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
14306#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
14307#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
14309/******************** Bit definition for USB_OTG_CID register ********************/
14310#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
14311#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
14312#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
14314/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
14315#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
14316#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
14317#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
14318#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
14319#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
14320#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
14321#define USB_OTG_GLPMCFG_BESL_Pos (2U)
14322#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
14323#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
14324#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
14325#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
14326#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
14327#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
14328#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
14329#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
14330#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
14331#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
14332#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
14333#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
14334#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
14335#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
14336#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
14337#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
14338#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
14339#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
14340#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
14341#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
14342#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
14343#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
14344#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
14345#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
14346#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
14347#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
14348#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
14349#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
14350#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
14351#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
14352#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
14353#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
14354#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
14355#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
14356#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
14357#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
14358#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
14359#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
14361/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
14362#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
14363#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
14364#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
14365#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
14366#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
14367#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
14368#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
14369#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
14370#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
14371#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
14372#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
14373#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
14374#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
14375#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
14376#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
14377#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
14378#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
14379#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
14380#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
14381#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
14382#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
14383#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
14384#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
14385#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
14386#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
14387#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
14388#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
14390/******************** Bit definition for USB_OTG_HPRT register ********************/
14391#define USB_OTG_HPRT_PCSTS_Pos (0U)
14392#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
14393#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
14394#define USB_OTG_HPRT_PCDET_Pos (1U)
14395#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
14396#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
14397#define USB_OTG_HPRT_PENA_Pos (2U)
14398#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
14399#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
14400#define USB_OTG_HPRT_PENCHNG_Pos (3U)
14401#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
14402#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
14403#define USB_OTG_HPRT_POCA_Pos (4U)
14404#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
14405#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
14406#define USB_OTG_HPRT_POCCHNG_Pos (5U)
14407#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
14408#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
14409#define USB_OTG_HPRT_PRES_Pos (6U)
14410#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
14411#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
14412#define USB_OTG_HPRT_PSUSP_Pos (7U)
14413#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
14414#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
14415#define USB_OTG_HPRT_PRST_Pos (8U)
14416#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
14417#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
14419#define USB_OTG_HPRT_PLSTS_Pos (10U)
14420#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
14421#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
14422#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
14423#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
14424#define USB_OTG_HPRT_PPWR_Pos (12U)
14425#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
14426#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
14428#define USB_OTG_HPRT_PTCTL_Pos (13U)
14429#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
14430#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
14431#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
14432#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
14433#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
14434#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
14436#define USB_OTG_HPRT_PSPD_Pos (17U)
14437#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
14438#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
14439#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
14440#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
14442/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
14443#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
14444#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
14445#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
14446#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
14447#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
14448#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
14449#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
14450#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
14451#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
14452#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
14453#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
14454#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
14455#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
14456#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
14457#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
14458#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
14459#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
14460#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
14461#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
14462#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
14463#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
14464#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
14465#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
14466#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
14467#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
14468#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
14469#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
14470#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
14471#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
14472#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
14473#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
14474#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
14475#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
14477/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
14478#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
14479#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
14480#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
14481#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
14482#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
14483#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
14485/******************** Bit definition for USB_OTG_DIEPCTL register ********************/
14486#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
14487#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
14488#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
14489#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
14490#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
14491#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
14492#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
14493#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
14494#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
14495#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
14496#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
14497#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
14499#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
14500#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14501#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
14502#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14503#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
14504#define USB_OTG_DIEPCTL_STALL_Pos (21U)
14505#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
14506#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
14508#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
14509#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14510#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
14511#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14512#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14513#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14514#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
14515#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
14516#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
14517#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
14518#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
14519#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
14520#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
14521#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
14522#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
14523#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
14524#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
14525#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
14526#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
14527#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
14528#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
14529#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
14530#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
14531#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
14532#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
14534/******************** Bit definition for USB_OTG_HCCHAR register ********************/
14535#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
14536#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
14537#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
14539#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
14540#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
14541#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
14542#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
14543#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
14544#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
14545#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
14546#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
14547#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
14548#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
14549#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
14550#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
14551#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
14553#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
14554#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
14555#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
14556#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
14557#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
14559#define USB_OTG_HCCHAR_MC_Pos (20U)
14560#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
14561#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
14562#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
14563#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
14565#define USB_OTG_HCCHAR_DAD_Pos (22U)
14566#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
14567#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
14568#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
14569#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
14570#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
14571#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
14572#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
14573#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
14574#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
14575#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
14576#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
14577#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
14578#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
14579#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
14580#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
14581#define USB_OTG_HCCHAR_CHENA_Pos (31U)
14582#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
14583#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
14585/******************** Bit definition for USB_OTG_HCSPLT register ********************/
14586
14587#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
14588#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
14589#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
14590#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14591#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14592#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14593#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14594#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14595#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14596#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
14598#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
14599#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
14600#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
14601#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14602#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14603#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14604#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14605#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14606#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14607#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
14609#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
14610#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14611#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
14612#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14613#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
14614#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
14615#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
14616#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
14617#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
14618#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
14619#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
14621/******************** Bit definition for USB_OTG_HCINT register ********************/
14622#define USB_OTG_HCINT_XFRC_Pos (0U)
14623#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
14624#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
14625#define USB_OTG_HCINT_CHH_Pos (1U)
14626#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
14627#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
14628#define USB_OTG_HCINT_AHBERR_Pos (2U)
14629#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
14630#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
14631#define USB_OTG_HCINT_STALL_Pos (3U)
14632#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
14633#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
14634#define USB_OTG_HCINT_NAK_Pos (4U)
14635#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
14636#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
14637#define USB_OTG_HCINT_ACK_Pos (5U)
14638#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
14639#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
14640#define USB_OTG_HCINT_NYET_Pos (6U)
14641#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
14642#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
14643#define USB_OTG_HCINT_TXERR_Pos (7U)
14644#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
14645#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
14646#define USB_OTG_HCINT_BBERR_Pos (8U)
14647#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
14648#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
14649#define USB_OTG_HCINT_FRMOR_Pos (9U)
14650#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
14651#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
14652#define USB_OTG_HCINT_DTERR_Pos (10U)
14653#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
14654#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
14656/******************** Bit definition for USB_OTG_DIEPINT register ********************/
14657#define USB_OTG_DIEPINT_XFRC_Pos (0U)
14658#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
14659#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
14660#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
14661#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
14662#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
14663#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
14664#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
14665#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
14666#define USB_OTG_DIEPINT_TOC_Pos (3U)
14667#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
14668#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
14669#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
14670#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
14671#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
14672#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
14673#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
14674#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
14675#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
14676#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
14677#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
14678#define USB_OTG_DIEPINT_TXFE_Pos (7U)
14679#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
14680#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
14681#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
14682#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
14683#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
14684#define USB_OTG_DIEPINT_BNA_Pos (9U)
14685#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
14686#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
14687#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
14688#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
14689#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
14690#define USB_OTG_DIEPINT_BERR_Pos (12U)
14691#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
14692#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
14693#define USB_OTG_DIEPINT_NAK_Pos (13U)
14694#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
14695#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
14697/******************** Bit definition for USB_OTG_HCINTMSK register ********************/
14698#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
14699#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
14700#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
14701#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
14702#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
14703#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
14704#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
14705#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
14706#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
14707#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
14708#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
14709#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
14710#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
14711#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
14712#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
14713#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
14714#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
14715#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
14716#define USB_OTG_HCINTMSK_NYET_Pos (6U)
14717#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
14718#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
14719#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
14720#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
14721#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
14722#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
14723#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
14724#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
14725#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
14726#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
14727#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
14728#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
14729#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
14730#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
14732/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
14733
14734#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
14735#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
14736#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
14737#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
14738#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
14739#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
14740#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
14741#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
14742#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
14743/******************** Bit definition for USB_OTG_HCTSIZ register ********************/
14744#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
14745#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
14746#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
14747#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
14748#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
14749#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
14750#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
14751#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
14752#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
14753#define USB_OTG_HCTSIZ_DPID_Pos (29U)
14754#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
14755#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
14756#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
14757#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
14759/******************** Bit definition for USB_OTG_DIEPDMA register ********************/
14760#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
14761#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
14762#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
14764/******************** Bit definition for USB_OTG_HCDMA register ********************/
14765#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
14766#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
14767#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
14769/******************** Bit definition for USB_OTG_DTXFSTS register ********************/
14770#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
14771#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
14772#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
14774/******************** Bit definition for USB_OTG_DIEPTXF register ********************/
14775#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
14776#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
14777#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
14778#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
14779#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
14780#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
14782/******************** Bit definition for USB_OTG_DOEPCTL register ********************/
14783#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
14784#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
14785#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
14786#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
14787#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
14788#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
14789#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
14790#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
14791#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
14792#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
14793#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
14794#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
14795#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
14796#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
14797#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
14798#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
14799#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14800#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
14801#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14802#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
14803#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
14804#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
14805#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
14806#define USB_OTG_DOEPCTL_STALL_Pos (21U)
14807#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
14808#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
14809#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
14810#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
14811#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
14812#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
14813#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
14814#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
14815#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
14816#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
14817#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
14818#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
14819#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
14820#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
14822/******************** Bit definition for USB_OTG_DOEPINT register ********************/
14823#define USB_OTG_DOEPINT_XFRC_Pos (0U)
14824#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
14825#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
14826#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
14827#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
14828#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
14829#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
14830#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
14831#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
14832#define USB_OTG_DOEPINT_STUP_Pos (3U)
14833#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
14834#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
14835#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
14836#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
14837#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
14838#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
14839#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
14840#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
14841#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
14842#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
14843#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
14844#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
14845#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
14846#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
14847#define USB_OTG_DOEPINT_NAK_Pos (13U)
14848#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
14849#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
14850#define USB_OTG_DOEPINT_NYET_Pos (14U)
14851#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
14852#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
14853#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
14854#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
14855#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
14857/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
14858#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
14859#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
14860#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
14861#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
14862#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
14863#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
14865#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
14866#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
14867#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
14868#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
14869#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
14871/******************** Bit definition for PCGCCTL register ********************/
14872#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
14873#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
14874#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
14875#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
14876#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
14877#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
14878#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
14879#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
14880#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
14897/******************************* ADC Instances ********************************/
14898#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
14899 ((__INSTANCE__) == ADC2) || \
14900 ((__INSTANCE__) == ADC3))
14901#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
14902
14903#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
14904
14905/******************************* CAN Instances ********************************/
14906#define IS_CAN_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CAN1)
14907/******************************* CRC Instances ********************************/
14908#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
14909
14910/******************************* DAC Instances ********************************/
14911#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)
14912
14913
14914
14915
14916/******************************** DMA Instances *******************************/
14917#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
14918 ((__INSTANCE__) == DMA1_Stream1) || \
14919 ((__INSTANCE__) == DMA1_Stream2) || \
14920 ((__INSTANCE__) == DMA1_Stream3) || \
14921 ((__INSTANCE__) == DMA1_Stream4) || \
14922 ((__INSTANCE__) == DMA1_Stream5) || \
14923 ((__INSTANCE__) == DMA1_Stream6) || \
14924 ((__INSTANCE__) == DMA1_Stream7) || \
14925 ((__INSTANCE__) == DMA2_Stream0) || \
14926 ((__INSTANCE__) == DMA2_Stream1) || \
14927 ((__INSTANCE__) == DMA2_Stream2) || \
14928 ((__INSTANCE__) == DMA2_Stream3) || \
14929 ((__INSTANCE__) == DMA2_Stream4) || \
14930 ((__INSTANCE__) == DMA2_Stream5) || \
14931 ((__INSTANCE__) == DMA2_Stream6) || \
14932 ((__INSTANCE__) == DMA2_Stream7))
14933
14934/******************************* GPIO Instances *******************************/
14935#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
14936 ((__INSTANCE__) == GPIOB) || \
14937 ((__INSTANCE__) == GPIOC) || \
14938 ((__INSTANCE__) == GPIOD) || \
14939 ((__INSTANCE__) == GPIOE) || \
14940 ((__INSTANCE__) == GPIOF) || \
14941 ((__INSTANCE__) == GPIOG) || \
14942 ((__INSTANCE__) == GPIOH) || \
14943 ((__INSTANCE__) == GPIOI))
14944
14945#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
14946 ((__INSTANCE__) == GPIOB) || \
14947 ((__INSTANCE__) == GPIOC) || \
14948 ((__INSTANCE__) == GPIOD) || \
14949 ((__INSTANCE__) == GPIOE) || \
14950 ((__INSTANCE__) == GPIOF) || \
14951 ((__INSTANCE__) == GPIOG) || \
14952 ((__INSTANCE__) == GPIOH) || \
14953 ((__INSTANCE__) == GPIOI))
14954
14955
14956/****************************** QSPI Instances *********************************/
14957#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
14958
14959
14960/******************************** I2C Instances *******************************/
14961#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
14962 ((__INSTANCE__) == I2C2) || \
14963 ((__INSTANCE__) == I2C3))
14964
14965/****************************** SMBUS Instances *******************************/
14966#define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
14967 ((__INSTANCE__) == I2C2) || \
14968 ((__INSTANCE__) == I2C3))
14969
14970
14971/******************************** I2S Instances *******************************/
14972#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
14973 ((__INSTANCE__) == SPI2) || \
14974 ((__INSTANCE__) == SPI3))
14975
14976/******************************* LPTIM Instances ********************************/
14977#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
14978
14979
14980
14981
14982
14983/******************************* RNG Instances ********************************/
14984#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
14985
14986/****************************** RTC Instances *********************************/
14987#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
14988
14989/******************************* SAI Instances ********************************/
14990#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
14991 ((__PERIPH__) == SAI1_Block_B) || \
14992 ((__PERIPH__) == SAI2_Block_A) || \
14993 ((__PERIPH__) == SAI2_Block_B))
14994/* Legacy define */
14995#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
14996
14997/******************************** SDMMC Instances *******************************/
14998#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
14999 ((__INSTANCE__) == SDMMC2))
15000
15001
15002/******************************** SPI Instances *******************************/
15003#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
15004 ((__INSTANCE__) == SPI2) || \
15005 ((__INSTANCE__) == SPI3) || \
15006 ((__INSTANCE__) == SPI4) || \
15007 ((__INSTANCE__) == SPI5))
15008
15009/****************** TIM Instances : All supported instances *******************/
15010#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15011 ((__INSTANCE__) == TIM2) || \
15012 ((__INSTANCE__) == TIM3) || \
15013 ((__INSTANCE__) == TIM4) || \
15014 ((__INSTANCE__) == TIM5) || \
15015 ((__INSTANCE__) == TIM6) || \
15016 ((__INSTANCE__) == TIM7) || \
15017 ((__INSTANCE__) == TIM8) || \
15018 ((__INSTANCE__) == TIM9) || \
15019 ((__INSTANCE__) == TIM10) || \
15020 ((__INSTANCE__) == TIM11) || \
15021 ((__INSTANCE__) == TIM12) || \
15022 ((__INSTANCE__) == TIM13) || \
15023 ((__INSTANCE__) == TIM14))
15024
15025/****************** TIM Instances : supporting 32 bits counter ****************/
15026#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
15027 ((__INSTANCE__) == TIM5))
15028
15029/****************** TIM Instances : supporting the break function *************/
15030#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15031 ((INSTANCE) == TIM8))
15032
15033/************** TIM Instances : supporting Break source selection *************/
15034#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15035 ((INSTANCE) == TIM8))
15036
15037/****************** TIM Instances : supporting 2 break inputs *****************/
15038#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
15039 ((INSTANCE) == TIM8))
15040
15041/************* TIM Instances : at least 1 capture/compare channel *************/
15042#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15043 ((__INSTANCE__) == TIM2) || \
15044 ((__INSTANCE__) == TIM3) || \
15045 ((__INSTANCE__) == TIM4) || \
15046 ((__INSTANCE__) == TIM5) || \
15047 ((__INSTANCE__) == TIM8) || \
15048 ((__INSTANCE__) == TIM9) || \
15049 ((__INSTANCE__) == TIM10) || \
15050 ((__INSTANCE__) == TIM11) || \
15051 ((__INSTANCE__) == TIM12) || \
15052 ((__INSTANCE__) == TIM13) || \
15053 ((__INSTANCE__) == TIM14))
15054
15055/************ TIM Instances : at least 2 capture/compare channels *************/
15056#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15057 ((__INSTANCE__) == TIM2) || \
15058 ((__INSTANCE__) == TIM3) || \
15059 ((__INSTANCE__) == TIM4) || \
15060 ((__INSTANCE__) == TIM5) || \
15061 ((__INSTANCE__) == TIM8) || \
15062 ((__INSTANCE__) == TIM9) || \
15063 ((__INSTANCE__) == TIM12))
15064
15065/************ TIM Instances : at least 3 capture/compare channels *************/
15066#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15067 ((__INSTANCE__) == TIM2) || \
15068 ((__INSTANCE__) == TIM3) || \
15069 ((__INSTANCE__) == TIM4) || \
15070 ((__INSTANCE__) == TIM5) || \
15071 ((__INSTANCE__) == TIM8))
15072
15073/************ TIM Instances : at least 4 capture/compare channels *************/
15074#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15075 ((__INSTANCE__) == TIM2) || \
15076 ((__INSTANCE__) == TIM3) || \
15077 ((__INSTANCE__) == TIM4) || \
15078 ((__INSTANCE__) == TIM5) || \
15079 ((__INSTANCE__) == TIM8))
15080
15081/****************** TIM Instances : at least 5 capture/compare channels *******/
15082#define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15083 ((__INSTANCE__) == TIM8))
15084
15085/****************** TIM Instances : at least 6 capture/compare channels *******/
15086#define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15087 ((__INSTANCE__) == TIM8))
15088
15089/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
15090#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15091 ((__INSTANCE__) == TIM8))
15092
15093/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
15094#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15095 ((__INSTANCE__) == TIM8) || \
15096 ((__INSTANCE__) == TIM2) || \
15097 ((__INSTANCE__) == TIM3) || \
15098 ((__INSTANCE__) == TIM4) || \
15099 ((__INSTANCE__) == TIM5) || \
15100 ((__INSTANCE__) == TIM6) || \
15101 ((__INSTANCE__) == TIM7))
15102
15103/************ TIM Instances : DMA requests generation (CCxDE) *****************/
15104#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15105 ((__INSTANCE__) == TIM2) || \
15106 ((__INSTANCE__) == TIM3) || \
15107 ((__INSTANCE__) == TIM4) || \
15108 ((__INSTANCE__) == TIM5) || \
15109 ((__INSTANCE__) == TIM8))
15110
15111/******************** TIM Instances : DMA burst feature ***********************/
15112#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15113 ((__INSTANCE__) == TIM2) || \
15114 ((__INSTANCE__) == TIM3) || \
15115 ((__INSTANCE__) == TIM4) || \
15116 ((__INSTANCE__) == TIM5) || \
15117 ((__INSTANCE__) == TIM8))
15118
15119/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
15120#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
15121 (((__INSTANCE__) == TIM1) || \
15122 ((__INSTANCE__) == TIM8))
15123
15124/****************** TIM Instances : supporting counting mode selection ********/
15125#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15126 ((__INSTANCE__) == TIM2) || \
15127 ((__INSTANCE__) == TIM3) || \
15128 ((__INSTANCE__) == TIM4) || \
15129 ((__INSTANCE__) == TIM5) || \
15130 ((__INSTANCE__) == TIM8))
15131
15132/****************** TIM Instances : supporting encoder interface **************/
15133#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15134 ((__INSTANCE__) == TIM2) || \
15135 ((__INSTANCE__) == TIM3) || \
15136 ((__INSTANCE__) == TIM4) || \
15137 ((__INSTANCE__) == TIM5) || \
15138 ((__INSTANCE__) == TIM8))
15139
15140/****************** TIM Instances : supporting OCxREF clear *******************/
15141#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
15142 (((__INSTANCE__) == TIM2) || \
15143 ((__INSTANCE__) == TIM3) || \
15144 ((__INSTANCE__) == TIM4) || \
15145 ((__INSTANCE__) == TIM5))
15146
15147/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
15148#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
15149 (((__INSTANCE__) == TIM1) || \
15150 ((__INSTANCE__) == TIM2) || \
15151 ((__INSTANCE__) == TIM3) || \
15152 ((__INSTANCE__) == TIM4) || \
15153 ((__INSTANCE__) == TIM5) || \
15154 ((__INSTANCE__) == TIM8))
15155
15156/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
15157#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
15158 (((__INSTANCE__) == TIM1) || \
15159 ((__INSTANCE__) == TIM2) || \
15160 ((__INSTANCE__) == TIM3) || \
15161 ((__INSTANCE__) == TIM4) || \
15162 ((__INSTANCE__) == TIM5) || \
15163 ((__INSTANCE__) == TIM8))
15164
15165/******************** TIM Instances : Advanced-control timers *****************/
15166#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15167 ((__INSTANCE__) == TIM8))
15168
15169/******************* TIM Instances : Timer input XOR function *****************/
15170#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15171 ((__INSTANCE__) == TIM2) || \
15172 ((__INSTANCE__) == TIM3) || \
15173 ((__INSTANCE__) == TIM4) || \
15174 ((__INSTANCE__) == TIM5) || \
15175 ((__INSTANCE__) == TIM8))
15176
15177/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
15178#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15179 ((__INSTANCE__) == TIM2) || \
15180 ((__INSTANCE__) == TIM3) || \
15181 ((__INSTANCE__) == TIM4) || \
15182 ((__INSTANCE__) == TIM5) || \
15183 ((__INSTANCE__) == TIM6) || \
15184 ((__INSTANCE__) == TIM7) || \
15185 ((__INSTANCE__) == TIM8))
15186
15187/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
15188#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15189 ((__INSTANCE__) == TIM2) || \
15190 ((__INSTANCE__) == TIM3) || \
15191 ((__INSTANCE__) == TIM4) || \
15192 ((__INSTANCE__) == TIM5) || \
15193 ((__INSTANCE__) == TIM8) || \
15194 ((__INSTANCE__) == TIM9) || \
15195 ((__INSTANCE__) == TIM12))
15196
15197/***************** TIM Instances : external trigger input available ************/
15198#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15199 ((__INSTANCE__) == TIM2) || \
15200 ((__INSTANCE__) == TIM3) || \
15201 ((__INSTANCE__) == TIM4) || \
15202 ((__INSTANCE__) == TIM5) || \
15203 ((__INSTANCE__) == TIM8))
15204
15205/****************** TIM Instances : remapping capability **********************/
15206#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
15207 ((__INSTANCE__) == TIM5) || \
15208 ((__INSTANCE__) == TIM11))
15209
15210/******************* TIM Instances : output(s) available **********************/
15211#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
15212 ((((__INSTANCE__) == TIM1) && \
15213 (((__CHANNEL__) == TIM_CHANNEL_1) || \
15214 ((__CHANNEL__) == TIM_CHANNEL_2) || \
15215 ((__CHANNEL__) == TIM_CHANNEL_3) || \
15216 ((__CHANNEL__) == TIM_CHANNEL_4) || \
15217 ((__CHANNEL__) == TIM_CHANNEL_5) || \
15218 ((__CHANNEL__) == TIM_CHANNEL_6))) \
15219 || \
15220 (((__INSTANCE__) == TIM2) && \
15221 (((__CHANNEL__) == TIM_CHANNEL_1) || \
15222 ((__CHANNEL__) == TIM_CHANNEL_2) || \
15223 ((__CHANNEL__) == TIM_CHANNEL_3) || \
15224 ((__CHANNEL__) == TIM_CHANNEL_4))) \
15225 || \
15226 (((__INSTANCE__) == TIM3) && \
15227 (((__CHANNEL__) == TIM_CHANNEL_1) || \
15228 ((__CHANNEL__) == TIM_CHANNEL_2) || \
15229 ((__CHANNEL__) == TIM_CHANNEL_3) || \
15230 ((__CHANNEL__) == TIM_CHANNEL_4))) \
15231 || \
15232 (((__INSTANCE__) == TIM4) && \
15233 (((__CHANNEL__) == TIM_CHANNEL_1) || \
15234 ((__CHANNEL__) == TIM_CHANNEL_2) || \
15235 ((__CHANNEL__) == TIM_CHANNEL_3) || \
15236 ((__CHANNEL__) == TIM_CHANNEL_4))) \
15237 || \
15238 (((__INSTANCE__) == TIM5) && \
15239 (((__CHANNEL__) == TIM_CHANNEL_1) || \
15240 ((__CHANNEL__) == TIM_CHANNEL_2) || \
15241 ((__CHANNEL__) == TIM_CHANNEL_3) || \
15242 ((__CHANNEL__) == TIM_CHANNEL_4))) \
15243 || \
15244 (((__INSTANCE__) == TIM8) && \
15245 (((__CHANNEL__) == TIM_CHANNEL_1) || \
15246 ((__CHANNEL__) == TIM_CHANNEL_2) || \
15247 ((__CHANNEL__) == TIM_CHANNEL_3) || \
15248 ((__CHANNEL__) == TIM_CHANNEL_4) || \
15249 ((__CHANNEL__) == TIM_CHANNEL_5) || \
15250 ((__CHANNEL__) == TIM_CHANNEL_6))) \
15251 || \
15252 (((__INSTANCE__) == TIM9) && \
15253 (((__CHANNEL__) == TIM_CHANNEL_1) || \
15254 ((__CHANNEL__) == TIM_CHANNEL_2))) \
15255 || \
15256 (((__INSTANCE__) == TIM10) && \
15257 (((__CHANNEL__) == TIM_CHANNEL_1))) \
15258 || \
15259 (((__INSTANCE__) == TIM11) && \
15260 (((__CHANNEL__) == TIM_CHANNEL_1))) \
15261 || \
15262 (((__INSTANCE__) == TIM12) && \
15263 (((__CHANNEL__) == TIM_CHANNEL_1) || \
15264 ((__CHANNEL__) == TIM_CHANNEL_2))) \
15265 || \
15266 (((__INSTANCE__) == TIM13) && \
15267 (((__CHANNEL__) == TIM_CHANNEL_1))) \
15268 || \
15269 (((__INSTANCE__) == TIM14) && \
15270 (((__CHANNEL__) == TIM_CHANNEL_1))))
15271
15272/************ TIM Instances : complementary output(s) available ***************/
15273#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
15274 ((((__INSTANCE__) == TIM1) && \
15275 (((__CHANNEL__) == TIM_CHANNEL_1) || \
15276 ((__CHANNEL__) == TIM_CHANNEL_2) || \
15277 ((__CHANNEL__) == TIM_CHANNEL_3))) \
15278 || \
15279 (((__INSTANCE__) == TIM8) && \
15280 (((__CHANNEL__) == TIM_CHANNEL_1) || \
15281 ((__CHANNEL__) == TIM_CHANNEL_2) || \
15282 ((__CHANNEL__) == TIM_CHANNEL_3))))
15283
15284/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
15285#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
15286 (((__INSTANCE__) == TIM1) || \
15287 ((__INSTANCE__) == TIM8) )
15288
15289/****************** TIM Instances : supporting clock division *****************/
15290#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15291 ((__INSTANCE__) == TIM2) || \
15292 ((__INSTANCE__) == TIM3) || \
15293 ((__INSTANCE__) == TIM4) || \
15294 ((__INSTANCE__) == TIM5) || \
15295 ((__INSTANCE__) == TIM8) || \
15296 ((__INSTANCE__) == TIM9) || \
15297 ((__INSTANCE__) == TIM10) || \
15298 ((__INSTANCE__) == TIM11) || \
15299 ((__INSTANCE__) == TIM12) || \
15300 ((__INSTANCE__) == TIM13) || \
15301 ((__INSTANCE__) == TIM14))
15302
15303/****************** TIM Instances : supporting repetition counter *************/
15304#define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15305 ((__INSTANCE__) == TIM8))
15306
15307/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
15308#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15309 ((__INSTANCE__) == TIM2) || \
15310 ((__INSTANCE__) == TIM3) || \
15311 ((__INSTANCE__) == TIM4) || \
15312 ((__INSTANCE__) == TIM5) || \
15313 ((__INSTANCE__) == TIM8) || \
15314 ((__INSTANCE__) == TIM9) || \
15315 ((__INSTANCE__) == TIM12))
15316
15317/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
15318#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15319 ((__INSTANCE__) == TIM2) || \
15320 ((__INSTANCE__) == TIM3) || \
15321 ((__INSTANCE__) == TIM4) || \
15322 ((__INSTANCE__) == TIM5) || \
15323 ((__INSTANCE__) == TIM8))
15324
15325/****************** TIM Instances : supporting Hall sensor interface **********/
15326#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15327 ((__INSTANCE__) == TIM2) || \
15328 ((__INSTANCE__) == TIM3) || \
15329 ((__INSTANCE__) == TIM4) || \
15330 ((__INSTANCE__) == TIM5) || \
15331 ((__INSTANCE__) == TIM8))
15332
15333/****************** TIM Instances : supporting commutation event generation ***/
15334#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
15335 ((__INSTANCE__) == TIM8))
15336
15337/******************** USART Instances : Synchronous mode **********************/
15338#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
15339 ((__INSTANCE__) == USART2) || \
15340 ((__INSTANCE__) == USART3) || \
15341 ((__INSTANCE__) == USART6))
15342
15343/******************** UART Instances : Asynchronous mode **********************/
15344#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
15345 ((__INSTANCE__) == USART2) || \
15346 ((__INSTANCE__) == USART3) || \
15347 ((__INSTANCE__) == UART4) || \
15348 ((__INSTANCE__) == UART5) || \
15349 ((__INSTANCE__) == USART6) || \
15350 ((__INSTANCE__) == UART7) || \
15351 ((__INSTANCE__) == UART8))
15352
15353/****************** UART Instances : Auto Baud Rate detection ****************/
15354#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
15355 ((__INSTANCE__) == USART2) || \
15356 ((__INSTANCE__) == USART3) || \
15357 ((__INSTANCE__) == USART6))
15358
15359/****************** UART Instances : Driver Enable *****************/
15360#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
15361 ((__INSTANCE__) == USART2) || \
15362 ((__INSTANCE__) == USART3) || \
15363 ((__INSTANCE__) == UART4) || \
15364 ((__INSTANCE__) == UART5) || \
15365 ((__INSTANCE__) == USART6) || \
15366 ((__INSTANCE__) == UART7) || \
15367 ((__INSTANCE__) == UART8))
15368
15369/******************** UART Instances : Half-Duplex mode **********************/
15370#define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
15371 ((__INSTANCE__) == USART2) || \
15372 ((__INSTANCE__) == USART3) || \
15373 ((__INSTANCE__) == UART4) || \
15374 ((__INSTANCE__) == UART5) || \
15375 ((__INSTANCE__) == USART6) || \
15376 ((__INSTANCE__) == UART7) || \
15377 ((__INSTANCE__) == UART8))
15378
15379/****************** UART Instances : Hardware Flow control ********************/
15380#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
15381 ((__INSTANCE__) == USART2) || \
15382 ((__INSTANCE__) == USART3) || \
15383 ((__INSTANCE__) == UART4) || \
15384 ((__INSTANCE__) == UART5) || \
15385 ((__INSTANCE__) == USART6) || \
15386 ((__INSTANCE__) == UART7) || \
15387 ((__INSTANCE__) == UART8))
15388
15389/******************** UART Instances : LIN mode **********************/
15390#define IS_UART_LIN_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
15391 ((__INSTANCE__) == USART2) || \
15392 ((__INSTANCE__) == USART3) || \
15393 ((__INSTANCE__) == UART4) || \
15394 ((__INSTANCE__) == UART5) || \
15395 ((__INSTANCE__) == USART6) || \
15396 ((__INSTANCE__) == UART7) || \
15397 ((__INSTANCE__) == UART8))
15398
15399/********************* UART Instances : Smart card mode ***********************/
15400#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
15401 ((__INSTANCE__) == USART2) || \
15402 ((__INSTANCE__) == USART3) || \
15403 ((__INSTANCE__) == USART6))
15404
15405/*********************** UART Instances : IRDA mode ***************************/
15406#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
15407 ((__INSTANCE__) == USART2) || \
15408 ((__INSTANCE__) == USART3) || \
15409 ((__INSTANCE__) == UART4) || \
15410 ((__INSTANCE__) == UART5) || \
15411 ((__INSTANCE__) == USART6) || \
15412 ((__INSTANCE__) == UART7) || \
15413 ((__INSTANCE__) == UART8))
15414
15415/****************************** IWDG Instances ********************************/
15416#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
15417
15418/****************************** WWDG Instances ********************************/
15419#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
15420
15421/*********************** PCD Instances ****************************************/
15422#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15423 ((INSTANCE) == USB_OTG_HS))
15424
15425/*********************** HCD Instances ****************************************/
15426#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
15427 ((INSTANCE) == USB_OTG_HS))
15428
15429/******************************************************************************/
15430/* For a painless codes migration between the STM32F7xx device product */
15431/* lines, the aliases defined below are put in place to overcome the */
15432/* differences in the interrupt handlers and IRQn definitions. */
15433/* No need to update developed interrupt code when moving across */
15434/* product lines within the same STM32F7 Family */
15435/******************************************************************************/
15436
15437/* Aliases for __IRQn */
15438#define HASH_RNG_IRQn RNG_IRQn
15439
15440/* Aliases for __IRQHandler */
15441#define HASH_RNG_IRQHandler RNG_IRQHandler
15442
15455#ifdef __cplusplus
15456}
15457#endif /* __cplusplus */
15458
15459#endif /* __STM32F722xx_H */
15460
15461
15462/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
__IO
#define __IO
Definition: core_armv8mbl.h:196
__I
#define __I
Definition: core_armv8mbl.h:193
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32F7xx Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f722xx.h:50
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32f722xx.h:58
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition: stm32f722xx.h:123
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32f722xx.h:69
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition: stm32f722xx.h:74
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition: stm32f722xx.h:83
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32f722xx.h:64
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition: stm32f722xx.h:132
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition: stm32f722xx.h:117
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition: stm32f722xx.h:126
UART7_IRQn
@ UART7_IRQn
Definition: stm32f722xx.h:137
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32f722xx.h:93
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32f722xx.h:94
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32f722xx.h:53
SAI1_IRQn
@ SAI1_IRQn
Definition: stm32f722xx.h:141
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32f722xx.h:91
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32f722xx.h:89
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition: stm32f722xx.h:127
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition: stm32f722xx.h:104
USART2_IRQn
@ USART2_IRQn
Definition: stm32f722xx.h:99
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition: stm32f722xx.h:120
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32f722xx.h:56
ADC_IRQn
@ ADC_IRQn
Definition: stm32f722xx.h:79
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32f722xx.h:112
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32f722xx.h:97
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32f722xx.h:116
UART8_IRQn
@ UART8_IRQn
Definition: stm32f722xx.h:138
RCC_IRQn
@ RCC_IRQn
Definition: stm32f722xx.h:66
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32f722xx.h:115
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition: stm32f722xx.h:131
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32f722xx.h:95
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition: stm32f722xx.h:143
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32f722xx.h:107
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32f722xx.h:55
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32f722xx.h:59
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32f722xx.h:130
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32f722xx.h:129
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32f722xx.h:54
SPI5_IRQn
@ SPI5_IRQn
Definition: stm32f722xx.h:140
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32f722xx.h:57
RNG_IRQn
@ RNG_IRQn
Definition: stm32f722xx.h:135
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32f722xx.h:65
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition: stm32f722xx.h:125
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32f722xx.h:61
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32f722xx.h:92
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32f722xx.h:90
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition: stm32f722xx.h:118
CAN1_TX_IRQn
@ CAN1_TX_IRQn
Definition: stm32f722xx.h:80
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition: stm32f722xx.h:133
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition: stm32f722xx.h:110
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition: stm32f722xx.h:72
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32f722xx.h:101
SPI4_IRQn
@ SPI4_IRQn
Definition: stm32f722xx.h:139
TIM1_UP_TIM10_IRQn
@ TIM1_UP_TIM10_IRQn
Definition: stm32f722xx.h:86
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32f722xx.h:84
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition: stm32f722xx.h:73
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition: stm32f722xx.h:144
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition: stm32f722xx.h:124
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition: stm32f722xx.h:103
FPU_IRQn
@ FPU_IRQn
Definition: stm32f722xx.h:136
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition: stm32f722xx.h:105
USART6_IRQn
@ USART6_IRQn
Definition: stm32f722xx.h:128
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32f722xx.h:96
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition: stm32f722xx.h:134
PVD_IRQn
@ PVD_IRQn
Definition: stm32f722xx.h:62
TIM1_TRG_COM_TIM11_IRQn
@ TIM1_TRG_COM_TIM11_IRQn
Definition: stm32f722xx.h:87
TIM1_BRK_TIM9_IRQn
@ TIM1_BRK_TIM9_IRQn
Definition: stm32f722xx.h:85
FMC_IRQn
@ FMC_IRQn
Definition: stm32f722xx.h:109
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32f722xx.h:67
CAN1_RX0_IRQn
@ CAN1_RX0_IRQn
Definition: stm32f722xx.h:81
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32f722xx.h:71
SAI2_IRQn
@ SAI2_IRQn
Definition: stm32f722xx.h:142
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition: stm32f722xx.h:119
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32f722xx.h:63
UART5_IRQn
@ UART5_IRQn
Definition: stm32f722xx.h:114
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition: stm32f722xx.h:77
ETH_IRQn
@ ETH_IRQn
Definition: stm32f722xx.h:122
USART1_IRQn
@ USART1_IRQn
Definition: stm32f722xx.h:98
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32f722xx.h:70
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32f722xx.h:52
UART4_IRQn
@ UART4_IRQn
Definition: stm32f722xx.h:113
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition: stm32f722xx.h:106
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32f722xx.h:68
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition: stm32f722xx.h:121
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32f722xx.h:111
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition: stm32f722xx.h:108
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition: stm32f722xx.h:76
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition: stm32f722xx.h:78
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32f722xx.h:88
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition: stm32f722xx.h:82
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition: stm32f722xx.h:75
SDMMC2_IRQn
@ SDMMC2_IRQn
Definition: stm32f722xx.h:145
USART3_IRQn
@ USART3_IRQn
Definition: stm32f722xx.h:100
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32f722xx.h:102
ADC_Common_TypeDef
Definition: stm32f722xx.h:201
ADC_Common_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f722xx.h:203
ADC_Common_TypeDef::CDR
__IO uint32_t CDR
Definition: stm32f722xx.h:204
ADC_Common_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f722xx.h:202
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f722xx.h:177
ADC_TypeDef::JOFR2
__IO uint32_t JOFR2
Definition: stm32f722xx.h:184
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32f722xx.h:193
ADC_TypeDef::HTR
__IO uint32_t HTR
Definition: stm32f722xx.h:187
ADC_TypeDef::JOFR4
__IO uint32_t JOFR4
Definition: stm32f722xx.h:186
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32f722xx.h:189
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition: stm32f722xx.h:195
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f722xx.h:197
ADC_TypeDef::JOFR1
__IO uint32_t JOFR1
Definition: stm32f722xx.h:183
ADC_TypeDef::JOFR3
__IO uint32_t JOFR3
Definition: stm32f722xx.h:185
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition: stm32f722xx.h:182
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32f722xx.h:192
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition: stm32f722xx.h:196
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition: stm32f722xx.h:191
ADC_TypeDef::LTR
__IO uint32_t LTR
Definition: stm32f722xx.h:188
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition: stm32f722xx.h:190
ADC_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f722xx.h:179
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition: stm32f722xx.h:194
ADC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f722xx.h:178
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32f722xx.h:181
ADC_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f722xx.h:180
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f722xx.h:226
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition: stm32f722xx.h:227
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition: stm32f722xx.h:230
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition: stm32f722xx.h:228
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition: stm32f722xx.h:229
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f722xx.h:238
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition: stm32f722xx.h:240
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition: stm32f722xx.h:239
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f722xx.h:214
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition: stm32f722xx.h:215
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition: stm32f722xx.h:218
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition: stm32f722xx.h:217
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition: stm32f722xx.h:216
CAN_TypeDef
Controller Area Network.
Definition: stm32f722xx.h:248
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition: stm32f722xx.h:253
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition: stm32f722xx.h:261
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32f722xx.h:249
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition: stm32f722xx.h:255
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f722xx.h:263
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition: stm32f722xx.h:256
CAN_TypeDef::IER
__IO uint32_t IER
Definition: stm32f722xx.h:254
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition: stm32f722xx.h:251
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition: stm32f722xx.h:262
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition: stm32f722xx.h:264
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition: stm32f722xx.h:268
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f722xx.h:267
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition: stm32f722xx.h:252
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition: stm32f722xx.h:250
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition: stm32f722xx.h:266
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f722xx.h:265
CRC_TypeDef
CRC calculation unit.
Definition: stm32f722xx.h:279
CRC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f722xx.h:280
CRC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f722xx.h:285
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition: stm32f722xx.h:281
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f722xx.h:283
CRC_TypeDef::POL
__IO uint32_t POL
Definition: stm32f722xx.h:287
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition: stm32f722xx.h:282
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f722xx.h:284
CRC_TypeDef::INIT
__IO uint32_t INIT
Definition: stm32f722xx.h:286
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32f722xx.h:295
DAC_TypeDef::DHR12RD
__IO uint32_t DHR12RD
Definition: stm32f722xx.h:304
DAC_TypeDef::DHR12L2
__IO uint32_t DHR12L2
Definition: stm32f722xx.h:302
DAC_TypeDef::DHR8R2
__IO uint32_t DHR8R2
Definition: stm32f722xx.h:303
DAC_TypeDef::DHR12R2
__IO uint32_t DHR12R2
Definition: stm32f722xx.h:301
DAC_TypeDef::SWTRIGR
__IO uint32_t SWTRIGR
Definition: stm32f722xx.h:297
DAC_TypeDef::DHR8RD
__IO uint32_t DHR8RD
Definition: stm32f722xx.h:306
DAC_TypeDef::DOR1
__IO uint32_t DOR1
Definition: stm32f722xx.h:307
DAC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f722xx.h:296
DAC_TypeDef::DOR2
__IO uint32_t DOR2
Definition: stm32f722xx.h:308
DAC_TypeDef::DHR12R1
__IO uint32_t DHR12R1
Definition: stm32f722xx.h:298
DAC_TypeDef::DHR12LD
__IO uint32_t DHR12LD
Definition: stm32f722xx.h:305
DAC_TypeDef::DHR8R1
__IO uint32_t DHR8R1
Definition: stm32f722xx.h:300
DAC_TypeDef::DHR12L1
__IO uint32_t DHR12L1
Definition: stm32f722xx.h:299
DAC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f722xx.h:309
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f722xx.h:318
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition: stm32f722xx.h:319
DBGMCU_TypeDef::APB2FZ
__IO uint32_t APB2FZ
Definition: stm32f722xx.h:322
DBGMCU_TypeDef::APB1FZ
__IO uint32_t APB1FZ
Definition: stm32f722xx.h:321
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition: stm32f722xx.h:320
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32f722xx.h:331
DMA_Stream_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32f722xx.h:337
DMA_Stream_TypeDef::M0AR
__IO uint32_t M0AR
Definition: stm32f722xx.h:335
DMA_Stream_TypeDef::CR
__IO uint32_t CR
Definition: stm32f722xx.h:332
DMA_Stream_TypeDef::M1AR
__IO uint32_t M1AR
Definition: stm32f722xx.h:336
DMA_Stream_TypeDef::PAR
__IO uint32_t PAR
Definition: stm32f722xx.h:334
DMA_Stream_TypeDef::NDTR
__IO uint32_t NDTR
Definition: stm32f722xx.h:333
DMA_TypeDef
Definition: stm32f722xx.h:341
DMA_TypeDef::LISR
__IO uint32_t LISR
Definition: stm32f722xx.h:342
DMA_TypeDef::HISR
__IO uint32_t HISR
Definition: stm32f722xx.h:343
DMA_TypeDef::LIFCR
__IO uint32_t LIFCR
Definition: stm32f722xx.h:344
DMA_TypeDef::HIFCR
__IO uint32_t HIFCR
Definition: stm32f722xx.h:345
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f722xx.h:354
EXTI_TypeDef::RTSR
__IO uint32_t RTSR
Definition: stm32f722xx.h:357
EXTI_TypeDef::EMR
__IO uint32_t EMR
Definition: stm32f722xx.h:356
EXTI_TypeDef::SWIER
__IO uint32_t SWIER
Definition: stm32f722xx.h:359
EXTI_TypeDef::FTSR
__IO uint32_t FTSR
Definition: stm32f722xx.h:358
EXTI_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f722xx.h:355
EXTI_TypeDef::PR
__IO uint32_t PR
Definition: stm32f722xx.h:360
FLASH_TypeDef
FLASH Registers.
Definition: stm32f722xx.h:368
FLASH_TypeDef::OPTCR1
__IO uint32_t OPTCR1
Definition: stm32f722xx.h:375
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition: stm32f722xx.h:370
FLASH_TypeDef::OPTCR2
__IO uint32_t OPTCR2
Definition: stm32f722xx.h:376
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition: stm32f722xx.h:369
FLASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32f722xx.h:373
FLASH_TypeDef::OPTCR
__IO uint32_t OPTCR
Definition: stm32f722xx.h:374
FLASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32f722xx.h:372
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition: stm32f722xx.h:371
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32f722xx.h:386
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32f722xx.h:395
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32f722xx.h:404
FMC_Bank3_TypeDef::PCR
__IO uint32_t PCR
Definition: stm32f722xx.h:405
FMC_Bank3_TypeDef::PMEM
__IO uint32_t PMEM
Definition: stm32f722xx.h:407
FMC_Bank3_TypeDef::ECCR
__IO uint32_t ECCR
Definition: stm32f722xx.h:410
FMC_Bank3_TypeDef::PATT
__IO uint32_t PATT
Definition: stm32f722xx.h:408
FMC_Bank3_TypeDef::SR
__IO uint32_t SR
Definition: stm32f722xx.h:406
FMC_Bank3_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f722xx.h:409
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5_6.
Definition: stm32f722xx.h:418
FMC_Bank5_6_TypeDef::SDCMR
__IO uint32_t SDCMR
Definition: stm32f722xx.h:421
FMC_Bank5_6_TypeDef::SDSR
__IO uint32_t SDSR
Definition: stm32f722xx.h:423
FMC_Bank5_6_TypeDef::SDRTR
__IO uint32_t SDRTR
Definition: stm32f722xx.h:422
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f722xx.h:432
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition: stm32f722xx.h:440
GPIO_TypeDef::MODER
__IO uint32_t MODER
Definition: stm32f722xx.h:433
GPIO_TypeDef::OSPEEDR
__IO uint32_t OSPEEDR
Definition: stm32f722xx.h:435
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32f722xx.h:437
GPIO_TypeDef::OTYPER
__IO uint32_t OTYPER
Definition: stm32f722xx.h:434
GPIO_TypeDef::PUPDR
__IO uint32_t PUPDR
Definition: stm32f722xx.h:436
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition: stm32f722xx.h:438
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition: stm32f722xx.h:439
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32f722xx.h:462
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32f722xx.h:465
I2C_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f722xx.h:470
I2C_TypeDef::TIMINGR
__IO uint32_t TIMINGR
Definition: stm32f722xx.h:467
I2C_TypeDef::TIMEOUTR
__IO uint32_t TIMEOUTR
Definition: stm32f722xx.h:468
I2C_TypeDef::RXDR
__IO uint32_t RXDR
Definition: stm32f722xx.h:472
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f722xx.h:463
I2C_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f722xx.h:469
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32f722xx.h:466
I2C_TypeDef::TXDR
__IO uint32_t TXDR
Definition: stm32f722xx.h:473
I2C_TypeDef::PECR
__IO uint32_t PECR
Definition: stm32f722xx.h:471
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f722xx.h:464
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f722xx.h:481
IWDG_TypeDef::KR
__IO uint32_t KR
Definition: stm32f722xx.h:482
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition: stm32f722xx.h:484
IWDG_TypeDef::WINR
__IO uint32_t WINR
Definition: stm32f722xx.h:486
IWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f722xx.h:485
IWDG_TypeDef::PR
__IO uint32_t PR
Definition: stm32f722xx.h:483
LPTIM_TypeDef
LPTIMIMER.
Definition: stm32f722xx.h:732
LPTIM_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f722xx.h:734
LPTIM_TypeDef::CMP
__IO uint32_t CMP
Definition: stm32f722xx.h:738
LPTIM_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f722xx.h:736
LPTIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32f722xx.h:740
LPTIM_TypeDef::IER
__IO uint32_t IER
Definition: stm32f722xx.h:735
LPTIM_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f722xx.h:733
LPTIM_TypeDef::CR
__IO uint32_t CR
Definition: stm32f722xx.h:737
LPTIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32f722xx.h:739
PWR_TypeDef
Power Control.
Definition: stm32f722xx.h:496
PWR_TypeDef::CSR2
__IO uint32_t CSR2
Definition: stm32f722xx.h:500
PWR_TypeDef::CSR1
__IO uint32_t CSR1
Definition: stm32f722xx.h:498
PWR_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f722xx.h:497
PWR_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f722xx.h:499
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32f722xx.h:679
QUADSPI_TypeDef::AR
__IO uint32_t AR
Definition: stm32f722xx.h:686
QUADSPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f722xx.h:688
QUADSPI_TypeDef::ABR
__IO uint32_t ABR
Definition: stm32f722xx.h:687
QUADSPI_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32f722xx.h:683
QUADSPI_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f722xx.h:685
QUADSPI_TypeDef::DLR
__IO uint32_t DLR
Definition: stm32f722xx.h:684
QUADSPI_TypeDef::PSMKR
__IO uint32_t PSMKR
Definition: stm32f722xx.h:689
QUADSPI_TypeDef::PSMAR
__IO uint32_t PSMAR
Definition: stm32f722xx.h:690
QUADSPI_TypeDef::PIR
__IO uint32_t PIR
Definition: stm32f722xx.h:691
QUADSPI_TypeDef::CR
__IO uint32_t CR
Definition: stm32f722xx.h:680
QUADSPI_TypeDef::LPTR
__IO uint32_t LPTR
Definition: stm32f722xx.h:692
QUADSPI_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32f722xx.h:681
QUADSPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f722xx.h:682
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f722xx.h:509
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition: stm32f722xx.h:535
RCC_TypeDef::AHB1ENR
__IO uint32_t AHB1ENR
Definition: stm32f722xx.h:521
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f722xx.h:512
RCC_TypeDef::AHB3RSTR
__IO uint32_t AHB3RSTR
Definition: stm32f722xx.h:516
RCC_TypeDef::AHB2LPENR
__IO uint32_t AHB2LPENR
Definition: stm32f722xx.h:529
RCC_TypeDef::PLLI2SCFGR
__IO uint32_t PLLI2SCFGR
Definition: stm32f722xx.h:539
RCC_TypeDef::AHB3LPENR
__IO uint32_t AHB3LPENR
Definition: stm32f722xx.h:530
RCC_TypeDef::AHB1RSTR
__IO uint32_t AHB1RSTR
Definition: stm32f722xx.h:514
RCC_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f722xx.h:524
RCC_TypeDef::AHB2ENR
__IO uint32_t AHB2ENR
Definition: stm32f722xx.h:522
RCC_TypeDef::AHB2RSTR
__IO uint32_t AHB2RSTR
Definition: stm32f722xx.h:515
RCC_TypeDef::APB1RSTR
__IO uint32_t APB1RSTR
Definition: stm32f722xx.h:518
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f722xx.h:536
RCC_TypeDef::CIR
__IO uint32_t CIR
Definition: stm32f722xx.h:513
RCC_TypeDef::DCKCFGR1
__IO uint32_t DCKCFGR1
Definition: stm32f722xx.h:541
RCC_TypeDef::AHB1LPENR
__IO uint32_t AHB1LPENR
Definition: stm32f722xx.h:528
RCC_TypeDef::SSCGR
__IO uint32_t SSCGR
Definition: stm32f722xx.h:538
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition: stm32f722xx.h:519
RCC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f722xx.h:510
RCC_TypeDef::APB2LPENR
__IO uint32_t APB2LPENR
Definition: stm32f722xx.h:533
RCC_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f722xx.h:531
RCC_TypeDef::APB1ENR
__IO uint32_t APB1ENR
Definition: stm32f722xx.h:525
RCC_TypeDef::PLLSAICFGR
__IO uint32_t PLLSAICFGR
Definition: stm32f722xx.h:540
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition: stm32f722xx.h:526
RCC_TypeDef::AHB3ENR
__IO uint32_t AHB3ENR
Definition: stm32f722xx.h:523
RCC_TypeDef::APB1LPENR
__IO uint32_t APB1LPENR
Definition: stm32f722xx.h:532
RCC_TypeDef::PLLCFGR
__IO uint32_t PLLCFGR
Definition: stm32f722xx.h:511
RCC_TypeDef::DCKCFGR2
__IO uint32_t DCKCFGR2
Definition: stm32f722xx.h:542
RCC_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f722xx.h:517
RNG_TypeDef
RNG.
Definition: stm32f722xx.h:781
RNG_TypeDef::DR
__IO uint32_t DR
Definition: stm32f722xx.h:784
RNG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f722xx.h:782
RNG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f722xx.h:783
RTC_TypeDef
Real-Time Clock.
Definition: stm32f722xx.h:551
RTC_TypeDef::TSTR
__IO uint32_t TSTR
Definition: stm32f722xx.h:564
RTC_TypeDef::BKP3R
__IO uint32_t BKP3R
Definition: stm32f722xx.h:575
RTC_TypeDef::TSSSR
__IO uint32_t TSSSR
Definition: stm32f722xx.h:566
RTC_TypeDef::BKP20R
__IO uint32_t BKP20R
Definition: stm32f722xx.h:592
RTC_TypeDef::BKP6R
__IO uint32_t BKP6R
Definition: stm32f722xx.h:578
RTC_TypeDef::SHIFTR
__IO uint32_t SHIFTR
Definition: stm32f722xx.h:563
RTC_TypeDef::BKP17R
__IO uint32_t BKP17R
Definition: stm32f722xx.h:589
RTC_TypeDef::BKP30R
__IO uint32_t BKP30R
Definition: stm32f722xx.h:602
RTC_TypeDef::BKP7R
__IO uint32_t BKP7R
Definition: stm32f722xx.h:579
RTC_TypeDef::CALR
__IO uint32_t CALR
Definition: stm32f722xx.h:567
RTC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f722xx.h:553
RTC_TypeDef::BKP0R
__IO uint32_t BKP0R
Definition: stm32f722xx.h:572
RTC_TypeDef::BKP26R
__IO uint32_t BKP26R
Definition: stm32f722xx.h:598
RTC_TypeDef::ALRMBR
__IO uint32_t ALRMBR
Definition: stm32f722xx.h:560
RTC_TypeDef::BKP19R
__IO uint32_t BKP19R
Definition: stm32f722xx.h:591
RTC_TypeDef::ALRMBSSR
__IO uint32_t ALRMBSSR
Definition: stm32f722xx.h:570
RTC_TypeDef::ALRMASSR
__IO uint32_t ALRMASSR
Definition: stm32f722xx.h:569
RTC_TypeDef::WPR
__IO uint32_t WPR
Definition: stm32f722xx.h:561
RTC_TypeDef::TR
__IO uint32_t TR
Definition: stm32f722xx.h:552
RTC_TypeDef::BKP18R
__IO uint32_t BKP18R
Definition: stm32f722xx.h:590
RTC_TypeDef::BKP9R
__IO uint32_t BKP9R
Definition: stm32f722xx.h:581
RTC_TypeDef::BKP29R
__IO uint32_t BKP29R
Definition: stm32f722xx.h:601
RTC_TypeDef::BKP24R
__IO uint32_t BKP24R
Definition: stm32f722xx.h:596
RTC_TypeDef::BKP13R
__IO uint32_t BKP13R
Definition: stm32f722xx.h:585
RTC_TypeDef::BKP12R
__IO uint32_t BKP12R
Definition: stm32f722xx.h:584
RTC_TypeDef::OR
__IO uint32_t OR
Definition: stm32f722xx.h:571
RTC_TypeDef::BKP31R
__IO uint32_t BKP31R
Definition: stm32f722xx.h:603
RTC_TypeDef::BKP25R
__IO uint32_t BKP25R
Definition: stm32f722xx.h:597
RTC_TypeDef::SSR
__IO uint32_t SSR
Definition: stm32f722xx.h:562
RTC_TypeDef::reserved
uint32_t reserved
Definition: stm32f722xx.h:558
RTC_TypeDef::BKP23R
__IO uint32_t BKP23R
Definition: stm32f722xx.h:595
RTC_TypeDef::BKP2R
__IO uint32_t BKP2R
Definition: stm32f722xx.h:574
RTC_TypeDef::BKP22R
__IO uint32_t BKP22R
Definition: stm32f722xx.h:594
RTC_TypeDef::BKP10R
__IO uint32_t BKP10R
Definition: stm32f722xx.h:582
RTC_TypeDef::BKP4R
__IO uint32_t BKP4R
Definition: stm32f722xx.h:576
RTC_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f722xx.h:555
RTC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f722xx.h:554
RTC_TypeDef::BKP5R
__IO uint32_t BKP5R
Definition: stm32f722xx.h:577
RTC_TypeDef::TAMPCR
__IO uint32_t TAMPCR
Definition: stm32f722xx.h:568
RTC_TypeDef::TSDR
__IO uint32_t TSDR
Definition: stm32f722xx.h:565
RTC_TypeDef::ALRMAR
__IO uint32_t ALRMAR
Definition: stm32f722xx.h:559
RTC_TypeDef::BKP8R
__IO uint32_t BKP8R
Definition: stm32f722xx.h:580
RTC_TypeDef::WUTR
__IO uint32_t WUTR
Definition: stm32f722xx.h:557
RTC_TypeDef::BKP14R
__IO uint32_t BKP14R
Definition: stm32f722xx.h:586
RTC_TypeDef::BKP11R
__IO uint32_t BKP11R
Definition: stm32f722xx.h:583
RTC_TypeDef::PRER
__IO uint32_t PRER
Definition: stm32f722xx.h:556
RTC_TypeDef::BKP27R
__IO uint32_t BKP27R
Definition: stm32f722xx.h:599
RTC_TypeDef::BKP16R
__IO uint32_t BKP16R
Definition: stm32f722xx.h:588
RTC_TypeDef::BKP21R
__IO uint32_t BKP21R
Definition: stm32f722xx.h:593
RTC_TypeDef::BKP1R
__IO uint32_t BKP1R
Definition: stm32f722xx.h:573
RTC_TypeDef::BKP15R
__IO uint32_t BKP15R
Definition: stm32f722xx.h:587
RTC_TypeDef::BKP28R
__IO uint32_t BKP28R
Definition: stm32f722xx.h:600
SAI_Block_TypeDef
Definition: stm32f722xx.h:617
SAI_Block_TypeDef::DR
__IO uint32_t DR
Definition: stm32f722xx.h:625
SAI_Block_TypeDef::CLRFR
__IO uint32_t CLRFR
Definition: stm32f722xx.h:624
SAI_Block_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f722xx.h:618
SAI_Block_TypeDef::SLOTR
__IO uint32_t SLOTR
Definition: stm32f722xx.h:621
SAI_Block_TypeDef::FRCR
__IO uint32_t FRCR
Definition: stm32f722xx.h:620
SAI_Block_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f722xx.h:622
SAI_Block_TypeDef::SR
__IO uint32_t SR
Definition: stm32f722xx.h:623
SAI_Block_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f722xx.h:619
SAI_TypeDef
Serial Audio Interface.
Definition: stm32f722xx.h:612
SAI_TypeDef::GCR
__IO uint32_t GCR
Definition: stm32f722xx.h:613
SDMMC_TypeDef
SD host Interface.
Definition: stm32f722xx.h:634
SDMMC_TypeDef::ARG
__IO uint32_t ARG
Definition: stm32f722xx.h:637
SDMMC_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f722xx.h:649
SDMMC_TypeDef::DTIMER
__IO uint32_t DTIMER
Definition: stm32f722xx.h:644
SDMMC_TypeDef::RESP3
__I uint32_t RESP3
Definition: stm32f722xx.h:642
SDMMC_TypeDef::DCOUNT
__I uint32_t DCOUNT
Definition: stm32f722xx.h:647
SDMMC_TypeDef::RESP2
__I uint32_t RESP2
Definition: stm32f722xx.h:641
SDMMC_TypeDef::MASK
__IO uint32_t MASK
Definition: stm32f722xx.h:650
SDMMC_TypeDef::DLEN
__IO uint32_t DLEN
Definition: stm32f722xx.h:645
SDMMC_TypeDef::POWER
__IO uint32_t POWER
Definition: stm32f722xx.h:635
SDMMC_TypeDef::FIFO
__IO uint32_t FIFO
Definition: stm32f722xx.h:654
SDMMC_TypeDef::STA
__I uint32_t STA
Definition: stm32f722xx.h:648
SDMMC_TypeDef::RESP1
__I uint32_t RESP1
Definition: stm32f722xx.h:640
SDMMC_TypeDef::DCTRL
__IO uint32_t DCTRL
Definition: stm32f722xx.h:646
SDMMC_TypeDef::CLKCR
__IO uint32_t CLKCR
Definition: stm32f722xx.h:636
SDMMC_TypeDef::RESPCMD
__I uint32_t RESPCMD
Definition: stm32f722xx.h:639
SDMMC_TypeDef::FIFOCNT
__I uint32_t FIFOCNT
Definition: stm32f722xx.h:652
SDMMC_TypeDef::RESP4
__I uint32_t RESP4
Definition: stm32f722xx.h:643
SDMMC_TypeDef::CMD
__IO uint32_t CMD
Definition: stm32f722xx.h:638
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f722xx.h:662
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition: stm32f722xx.h:668
SPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f722xx.h:666
SPI_TypeDef::I2SCFGR
__IO uint32_t I2SCFGR
Definition: stm32f722xx.h:670
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f722xx.h:663
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition: stm32f722xx.h:669
SPI_TypeDef::I2SPR
__IO uint32_t I2SPR
Definition: stm32f722xx.h:671
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition: stm32f722xx.h:667
SPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f722xx.h:665
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f722xx.h:664
SYSCFG_TypeDef
System configuration controller.
Definition: stm32f722xx.h:449
SYSCFG_TypeDef::CMPCR
__IO uint32_t CMPCR
Definition: stm32f722xx.h:454
SYSCFG_TypeDef::PMC
__IO uint32_t PMC
Definition: stm32f722xx.h:451
SYSCFG_TypeDef::MEMRMP
__IO uint32_t MEMRMP
Definition: stm32f722xx.h:450
TIM_TypeDef
TIM.
Definition: stm32f722xx.h:700
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition: stm32f722xx.h:704
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition: stm32f722xx.h:708
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition: stm32f722xx.h:709
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition: stm32f722xx.h:706
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition: stm32f722xx.h:716
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition: stm32f722xx.h:703
TIM_TypeDef::CCR5
__IO uint32_t CCR5
Definition: stm32f722xx.h:723
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition: stm32f722xx.h:718
TIM_TypeDef::CCR6
__IO uint32_t CCR6
Definition: stm32f722xx.h:724
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32f722xx.h:710
TIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32f722xx.h:721
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition: stm32f722xx.h:717
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition: stm32f722xx.h:711
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition: stm32f722xx.h:713
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f722xx.h:701
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition: stm32f722xx.h:720
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32f722xx.h:715
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32f722xx.h:714
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition: stm32f722xx.h:707
TIM_TypeDef::CCMR3
__IO uint32_t CCMR3
Definition: stm32f722xx.h:722
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32f722xx.h:712
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32f722xx.h:719
TIM_TypeDef::SR
__IO uint32_t SR
Definition: stm32f722xx.h:705
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f722xx.h:702
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f722xx.h:749
USART_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32f722xx.h:753
USART_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32f722xx.h:758
USART_TypeDef::TDR
__IO uint32_t TDR
Definition: stm32f722xx.h:760
USART_TypeDef::GTPR
__IO uint32_t GTPR
Definition: stm32f722xx.h:754
USART_TypeDef::RDR
__IO uint32_t RDR
Definition: stm32f722xx.h:759
USART_TypeDef::RQR
__IO uint32_t RQR
Definition: stm32f722xx.h:756
USART_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f722xx.h:750
USART_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f722xx.h:757
USART_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32f722xx.h:752
USART_TypeDef::RTOR
__IO uint32_t RTOR
Definition: stm32f722xx.h:755
USART_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f722xx.h:751
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32f722xx.h:827
USB_OTG_DeviceTypeDef::DEACHMSK
__IO uint32_t DEACHMSK
Definition: stm32f722xx.h:843
USB_OTG_DeviceTypeDef::DOEPMSK
__IO uint32_t DOEPMSK
Definition: stm32f722xx.h:833
USB_OTG_DeviceTypeDef::Reserved20
uint32_t Reserved20
Definition: stm32f722xx.h:836
USB_OTG_DeviceTypeDef::DOUTEP1MSK
__IO uint32_t DOUTEP1MSK
Definition: stm32f722xx.h:847
USB_OTG_DeviceTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f722xx.h:831
USB_OTG_DeviceTypeDef::DAINTMSK
__IO uint32_t DAINTMSK
Definition: stm32f722xx.h:835
USB_OTG_DeviceTypeDef::DIEPMSK
__IO uint32_t DIEPMSK
Definition: stm32f722xx.h:832
USB_OTG_DeviceTypeDef::DAINT
__IO uint32_t DAINT
Definition: stm32f722xx.h:834
USB_OTG_DeviceTypeDef::Reserved9
uint32_t Reserved9
Definition: stm32f722xx.h:837
USB_OTG_DeviceTypeDef::DSTS
__IO uint32_t DSTS
Definition: stm32f722xx.h:830
USB_OTG_DeviceTypeDef::DIEPEMPMSK
__IO uint32_t DIEPEMPMSK
Definition: stm32f722xx.h:841
USB_OTG_DeviceTypeDef::DCFG
__IO uint32_t DCFG
Definition: stm32f722xx.h:828
USB_OTG_DeviceTypeDef::Reserved40
uint32_t Reserved40
Definition: stm32f722xx.h:844
USB_OTG_DeviceTypeDef::DINEP1MSK
__IO uint32_t DINEP1MSK
Definition: stm32f722xx.h:845
USB_OTG_DeviceTypeDef::DTHRCTL
__IO uint32_t DTHRCTL
Definition: stm32f722xx.h:840
USB_OTG_DeviceTypeDef::DVBUSPULSE
__IO uint32_t DVBUSPULSE
Definition: stm32f722xx.h:839
USB_OTG_DeviceTypeDef::DCTL
__IO uint32_t DCTL
Definition: stm32f722xx.h:829
USB_OTG_DeviceTypeDef::DEACHINT
__IO uint32_t DEACHINT
Definition: stm32f722xx.h:842
USB_OTG_DeviceTypeDef::DVBUSDIS
__IO uint32_t DVBUSDIS
Definition: stm32f722xx.h:838
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32f722xx.h:795
USB_OTG_GlobalTypeDef::GRXSTSP
__IO uint32_t GRXSTSP
Definition: stm32f722xx.h:804
USB_OTG_GlobalTypeDef::GUSBCFG
__IO uint32_t GUSBCFG
Definition: stm32f722xx.h:799
USB_OTG_GlobalTypeDef::GRXFSIZ
__IO uint32_t GRXFSIZ
Definition: stm32f722xx.h:805
USB_OTG_GlobalTypeDef::Reserved6
uint32_t Reserved6
Definition: stm32f722xx.h:813
USB_OTG_GlobalTypeDef::GOTGCTL
__IO uint32_t GOTGCTL
Definition: stm32f722xx.h:796
USB_OTG_GlobalTypeDef::GLPMCFG
__IO uint32_t GLPMCFG
Definition: stm32f722xx.h:814
USB_OTG_GlobalTypeDef::GINTMSK
__IO uint32_t GINTMSK
Definition: stm32f722xx.h:802
USB_OTG_GlobalTypeDef::CID
__IO uint32_t CID
Definition: stm32f722xx.h:810
USB_OTG_GlobalTypeDef::HNPTXSTS
__IO uint32_t HNPTXSTS
Definition: stm32f722xx.h:807
USB_OTG_GlobalTypeDef::HPTXFSIZ
__IO uint32_t HPTXFSIZ
Definition: stm32f722xx.h:818
USB_OTG_GlobalTypeDef::DIEPTXF0_HNPTXFSIZ
__IO uint32_t DIEPTXF0_HNPTXFSIZ
Definition: stm32f722xx.h:806
USB_OTG_GlobalTypeDef::GRXSTSR
__IO uint32_t GRXSTSR
Definition: stm32f722xx.h:803
USB_OTG_GlobalTypeDef::GINTSTS
__IO uint32_t GINTSTS
Definition: stm32f722xx.h:801
USB_OTG_GlobalTypeDef::Reserved7
uint32_t Reserved7
Definition: stm32f722xx.h:815
USB_OTG_GlobalTypeDef::GAHBCFG
__IO uint32_t GAHBCFG
Definition: stm32f722xx.h:798
USB_OTG_GlobalTypeDef::GHWCFG3
__IO uint32_t GHWCFG3
Definition: stm32f722xx.h:812
USB_OTG_GlobalTypeDef::GDFIFOCFG
__IO uint32_t GDFIFOCFG
Definition: stm32f722xx.h:816
USB_OTG_GlobalTypeDef::GRSTCTL
__IO uint32_t GRSTCTL
Definition: stm32f722xx.h:800
USB_OTG_GlobalTypeDef::GOTGINT
__IO uint32_t GOTGINT
Definition: stm32f722xx.h:797
USB_OTG_GlobalTypeDef::GCCFG
__IO uint32_t GCCFG
Definition: stm32f722xx.h:809
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32f722xx.h:900
USB_OTG_HostChannelTypeDef::HCINT
__IO uint32_t HCINT
Definition: stm32f722xx.h:903
USB_OTG_HostChannelTypeDef::HCCHAR
__IO uint32_t HCCHAR
Definition: stm32f722xx.h:901
USB_OTG_HostChannelTypeDef::HCSPLT
__IO uint32_t HCSPLT
Definition: stm32f722xx.h:902
USB_OTG_HostChannelTypeDef::HCTSIZ
__IO uint32_t HCTSIZ
Definition: stm32f722xx.h:905
USB_OTG_HostChannelTypeDef::HCINTMSK
__IO uint32_t HCINTMSK
Definition: stm32f722xx.h:904
USB_OTG_HostChannelTypeDef::HCDMA
__IO uint32_t HCDMA
Definition: stm32f722xx.h:906
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32f722xx.h:886
USB_OTG_HostTypeDef::HFIR
__IO uint32_t HFIR
Definition: stm32f722xx.h:888
USB_OTG_HostTypeDef::HPTXSTS
__IO uint32_t HPTXSTS
Definition: stm32f722xx.h:891
USB_OTG_HostTypeDef::HAINTMSK
__IO uint32_t HAINTMSK
Definition: stm32f722xx.h:893
USB_OTG_HostTypeDef::HFNUM
__IO uint32_t HFNUM
Definition: stm32f722xx.h:889
USB_OTG_HostTypeDef::HAINT
__IO uint32_t HAINT
Definition: stm32f722xx.h:892
USB_OTG_HostTypeDef::HCFG
__IO uint32_t HCFG
Definition: stm32f722xx.h:887
USB_OTG_HostTypeDef::Reserved40C
uint32_t Reserved40C
Definition: stm32f722xx.h:890
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32f722xx.h:855
USB_OTG_INEndpointTypeDef::DIEPDMA
__IO uint32_t DIEPDMA
Definition: stm32f722xx.h:861
USB_OTG_INEndpointTypeDef::DIEPTSIZ
__IO uint32_t DIEPTSIZ
Definition: stm32f722xx.h:860
USB_OTG_INEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f722xx.h:859
USB_OTG_INEndpointTypeDef::DTXFSTS
__IO uint32_t DTXFSTS
Definition: stm32f722xx.h:862
USB_OTG_INEndpointTypeDef::DIEPINT
__IO uint32_t DIEPINT
Definition: stm32f722xx.h:858
USB_OTG_INEndpointTypeDef::Reserved18
uint32_t Reserved18
Definition: stm32f722xx.h:863
USB_OTG_INEndpointTypeDef::DIEPCTL
__IO uint32_t DIEPCTL
Definition: stm32f722xx.h:856
USB_OTG_INEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32f722xx.h:857
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32f722xx.h:871
USB_OTG_OUTEndpointTypeDef::Reserved0C
uint32_t Reserved0C
Definition: stm32f722xx.h:875
USB_OTG_OUTEndpointTypeDef::DOEPTSIZ
__IO uint32_t DOEPTSIZ
Definition: stm32f722xx.h:876
USB_OTG_OUTEndpointTypeDef::DOEPDMA
__IO uint32_t DOEPDMA
Definition: stm32f722xx.h:877
USB_OTG_OUTEndpointTypeDef::DOEPCTL
__IO uint32_t DOEPCTL
Definition: stm32f722xx.h:872
USB_OTG_OUTEndpointTypeDef::Reserved04
uint32_t Reserved04
Definition: stm32f722xx.h:873
USB_OTG_OUTEndpointTypeDef::DOEPINT
__IO uint32_t DOEPINT
Definition: stm32f722xx.h:874
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f722xx.h:769
WWDG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f722xx.h:770
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32f722xx.h:771
WWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f722xx.h:772
system_stm32f7xx.h
CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.
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